Cypress CY7C1512JV18, CY7C1514JV18, CY7C1510JV18 manual Package Diagram, Ball Fbga 15 x 17 x 1.40 mm

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CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

Package Diagram

Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195

TOP VIEW

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

	BOTTOM VIEW										PIN 1 CORNER
						Ø0.05 M C					PIN 1 CORNER
						Ø0.05 M C
						Ø0.25 M C A B
						Ø0.50		+0.14
						Ø0.50		(165X)
								-0.06
	11	10	9	8	7	6	5	4	3	2	1
											A
											B
	1.00										C
	1.00										D
											D
											E
											F
17.00±0.10	14.00										G
17.00±0.10	14.00										H
											J
											K
	7.00										L
	7.00										M
											M
											N
											P
											R
A								1.00
			5.00					1.00
			5.00
					10.00
	B			15.00±0.10

0.15(4X)

0.25 C

0.53±0.05

C 0.36

0.35±0.06	0.15 C
SEATING PLANE
	1.40 MAX.

NOTES :

SOLDER PAD TYPE : NON SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.65g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AD

51-85195-*A

Document #: 001-14435 Rev. *C

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1525JV18 Logic Block Diagram CY7C1510JV18Doff Logic Block Diagram CY7C1514JV18 Logic Block Diagram CY7C1512JV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1510JV18 8M x CY7C1525JV18 8M xWPS BWS CY7C1512JV18 4M xCY7C1514JV18 2M x Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleSram #1 Write Cycle Descriptions Truth TableRPS WPS BWS0 BWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Waveforms Power Up Sequence in QDR-II SramPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Capacitance AC Electrical CharacteristicsThermal Resistance AC Test Loads and WaveformsCypress Consortium Description 267 MHz 250 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingWrite Read Switching WaveformsWrite NOP Ordering Information Ball Fbga 15 x 17 x 1.40 mm Package DiagramVKN REV ECN no Issue ORIG. Description of Change DateVKN/AESA