Cypress CY7C1512JV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

Page 17

CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

Identification Register Definitions

Instruction Field

 

Value

 

Description

CY7C1510JV18

CY7C1525JV18

CY7C1512JV18

CY7C1514JV18

 

 

Revision Number

001

001

001

001

Version number.

(31:29)

 

 

 

 

 

Cypress Device ID

11010011010000100

11010011010001100

11010011010010100

11010011010100100

Defines the type of

(28:12)

 

 

 

 

SRAM.

Cypress JEDEC ID

00000110100

00000110100

00000110100

00000110100

Allows unique

(11:1)

 

 

 

 

identification of

 

 

 

 

 

SRAM vendor.

ID Register

1

1

1

1

Indicates the

Presence (0)

 

 

 

 

presence of an ID

 

 

 

 

 

register.

Scan Register Sizes

Register Name

Bit Size

Instruction

3

 

 

Bypass

1

 

 

ID

32

 

 

Boundary Scan

109

 

 

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

 

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures the input and output contents. Places the boundary scan register between TDI and

 

 

TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operation.

Document #: 001-14435 Rev. *C

Page 17 of 26

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1510JV18Logic Block Diagram CY7C1525JV18 Logic Block Diagram CY7C1514JV18 Logic Block Diagram CY7C1512JV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1510JV18 8M x CY7C1525JV18 8M xCY7C1514JV18 2M x CY7C1512JV18 4M xWPS BWS Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Sram #1 Application ExampleEcho Clocks Write Cycle Descriptions Truth TableRPS WPS BWS0 BWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderPower Up Waveforms Power Up Sequence in QDR-II SramPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics Capacitance AC Electrical CharacteristicsThermal Resistance AC Test Loads and WaveformsCypress Consortium Description 267 MHz 250 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingWrite NOP Switching WaveformsWrite Read Ordering Information Ball Fbga 15 x 17 x 1.40 mm Package DiagramVKN/AESA REV ECN no Issue ORIG. Description of Change DateVKN