Cypress CY7C1514JV18 manual TAP AC Switching Characteristics, TAP Timing and Test Conditions

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CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

TAP AC Switching Characteristics

Over the Operating Range [13, 14]

Parameter

Description

Min

Max

Unit

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH

20

 

ns

tTL

TCK Clock LOW

20

 

ns

Setup Times

 

 

 

 

 

 

 

 

 

tTMSS

TMS Setup to TCK Clock Rise

5

 

ns

tTDIS

TDI Setup to TCK Clock Rise

5

 

ns

tCS

Capture Setup to TCK Rise

5

 

ns

Hold Times

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Output Times

 

 

 

 

 

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions. [14]

Figure 2. TAP Timing and Test Conditions

 

 

 

0.9V

 

 

 

 

 

 

50Ω

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

Z0

= 50Ω

 

 

 

CL = 20 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES

1.8V

0.9V

0V

(a)GND

Test Clock

TCK

Test Mode Select

TMS

Test Data In

TDI

Test Data Out

TDO

tTH

tTMSS

tTDIS

tTL

tTCYC

tTMSH

tTDIH

tTDOV

 

 

 

t

 

 

 

 

 

 

 

 

TDOX

Notes

13.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

14.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document #: 001-14435 Rev. *C

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1525JV18 Logic Block Diagram CY7C1510JV18Doff Logic Block Diagram CY7C1512JV18 Logic Block Diagram CY7C1514JV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1510JV18 8M x CY7C1525JV18 8M xWPS BWS CY7C1512JV18 4M xCY7C1514JV18 2M x Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleSram #1 Truth Table Write Cycle DescriptionsRPS WPS BWS0 BWS1BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up WaveformsPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics CapacitanceThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Cypress Consortium Description 267 MHz 250 MHz UnitParameter Min Max DLL TimingWrite Read Switching WaveformsWrite NOP Ordering Information Package Diagram Ball Fbga 15 x 17 x 1.40 mmVKN REV ECN no Issue ORIG. Description of Change DateVKN/AESA