Cypress CY7C1514JV18 Pin Configuration, Ball Fbga 15 x 17 x 1.4 mm Pinout, CY7C1510JV18 8M x

Page 4

CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

Pin Configuration

The pin configuration for CY7C1510JV18, CY7C1525JV18, CY7C1512JV18, and CY7C1514JV18 follow. [1]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1510JV18 (8M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

1

NC/144M

A

A

CQ

CQ

WPS

NWS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q3

NWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

D3

D

NC

D4

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q4

VDDQ

VSS

VSS

VSS

VDDQ

NC

D2

Q2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q6

D6

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D0

N

NC

D7

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q7

A

A

C

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1525JV18 (8M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

NC

NC/144M

A

A

CQ

CQ

WPS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q4

BWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

D4

D

NC

D5

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q5

VDDQ

VSS

VSS

VSS

VDDQ

NC

D3

Q3

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q7

D7

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q1

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D1

N

NC

D8

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q8

A

A

C

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Note

1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document #: 001-14435 Rev. *C

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1525JV18 Logic Block Diagram CY7C1510JV18Doff Logic Block Diagram CY7C1512JV18 Logic Block Diagram CY7C1514JV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1510JV18 8M x CY7C1525JV18 8M xWPS BWS CY7C1512JV18 4M xCY7C1514JV18 2M x Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleSram #1 Truth Table Write Cycle DescriptionsRPS WPS BWS0 BWS1BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up WaveformsPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics CapacitanceThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Cypress Consortium Description 267 MHz 250 MHz UnitParameter Min Max DLL TimingWrite Read Switching WaveformsWrite NOP Ordering Information Package Diagram Ball Fbga 15 x 17 x 1.40 mmVKN REV ECN no Issue ORIG. Description of Change DateVKN/AESA