Cypress CY7C1336H manual Features, Functional Description1, Logic Block Diagram

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PRELIMINARYCY7C1336H

2-Mbit (64K x 32) Flow-Through Sync SRAM

Features

•64K x 32 common I/O

•3.3V core power supply

•3.3V I/O supply

•Fast clock-to-output times

—6.5 ns (133-MHz version)

—8.0 ns (100-MHz version)

•Provide high-performance 2-1-1-1 access rate

•User-selectable burst counter supporting Intel→ Pentium→ interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self-timed write

•Asynchronous output enable

•Supports 3.3V I/O level

•Offered in JEDEC-standard lead-free 100-pin TQFP package

•“ZZ” Sleep Mode option

Functional Description[1]

The CY7C1336H is a 64K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is

6.5ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1336H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1336H operates from a +3.3V core power supply while all outputs may operate with a +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram

ADDRESS

 

 

 

 

 

A0, A1, A

 

 

 

 

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

A[1:0]

 

 

 

 

 

 

 

 

 

 

 

ADV

 

BURST

Q1

 

 

 

 

CLK

 

COUNTER

 

 

 

 

 

 

 

AND LOGIC

 

 

 

 

 

 

CLR

Q0

 

 

 

 

 

 

 

 

 

 

 

ADSC

 

 

 

 

 

 

 

ADSP

 

 

 

 

 

 

 

 

 

DQD

DQD

 

 

 

 

BWD

 

BYTE

 

 

 

 

 

BYTE

 

 

 

 

 

 

WRITE REGISTER

 

 

 

 

 

 

WRITE REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

DQC

DQC

 

 

 

 

BWC

 

BYTE

 

 

 

 

 

BYTE

 

 

 

 

 

 

WRITE REGISTER

 

 

 

 

 

 

WRITE REGISTER

MEMORY

 

OUTPUT

DQs

 

 

 

SENSE

 

 

 

 

ARRAY

BUFFERS

 

 

 

 

DQB

AMPS

 

 

 

DQB

 

 

 

BWB

 

BYTE

 

 

 

 

 

 

 

 

 

 

 

BYTE

WRITE REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE REGISTER

 

 

 

 

 

 

 

 

DQA

 

 

 

 

BWA

 

DQA

BYTE

 

 

 

 

 

BYTE

WRITE REGISTER

 

 

 

 

BWE

 

 

 

 

 

 

WRITE REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

GW

 

 

 

 

 

INPUT

 

CE1

 

ENABLE

 

 

 

REGISTERS

 

 

 

 

 

 

 

 

REGISTER

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

ZZ

SLEEP

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

 

 

 

 

 

 

 

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

198 Champion Court • San Jose, CA 95134-1709

•

408-943-2600

Document #: 001-00210 Rev. *A

 

Revised February 6, 2006

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Contents Logic Block Diagram FeaturesFunctional Description1 Cypress Semiconductor CorporationSelection Guide Pin Configuration15CY7C1336H 133 MHz 100 MHz UnitPin Definitions Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description UsedFunction Truth Table for Read/Write 2BWE Operating Range Maximum RatingsAmbient RangeThermal Resistance9 Capacitance9AC Test Loads and Waveforms Parameter Description Test Conditions Tqfp UnitSwitching Characteristics Over the Operating Range 10 Read Cycle Timing16 Timing DiagramsCLK Write Cycle Timing16Adsc ADVAdsp Adsc Read/Write Timing16, 18Address Burst ReadZZ Mode Timing20 Ordering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Document History Issue Date Orig. Description of ChangeREV ECN no

CY7C1336H specifications

The Cypress CY7C1336H is a high-performance static random-access memory (SRAM) device that has gained recognition for its outstanding speed and reliability. This component is widely used in various high-performance applications including networking, telecommunications, and industrial control systems, where fast data storage and retrieval are critical.

One of the main features of the CY7C1336H is its high-speed operation, offering access times of as low as 10 nanoseconds. This makes it ideal for applications that require quick response times and efficient processing. The device operates with a supply voltage of 2.5V, which not only helps in reducing power consumption but also enables its use in newer low-voltage systems.

The CY7C1336H boasts a capacity of 1 megabit, organized in a configuration of 128K words by 8 bits. This allows it to store a significant amount of data while maintaining a compact footprint. In addition to its size, the device supports a burst mode, which enhances its efficiency in handling data transfer operations. This feature is particularly useful in applications requiring continuous data streaming, such as video processing or high-speed networking.

The memory technology employed in the CY7C1336H is known for its robustness and durability. Unlike DRAM, SRAM does not require periodic refreshing, which simplifies system design and improves overall performance. The device also features fast output enable and chip enable options, providing greater flexibility in controlling memory access and improving overall system response time.

In terms of packaging, the CY7C1336H is available in various forms including 32-pin SOJ and 44-pin TSOP packages, catering to diverse design requirements. Its compact packaging and low thermal characteristics make it suitable for space-constrained applications.

Another noteworthy characteristic of this SRAM is its inherent data integrity and reliability. With features such as on-chip parity generation and error checking capabilities, the CY7C1336H ensures that the data stored remains accurate and consistent over time.

Overall, the Cypress CY7C1336H delivers a blend of high speed, low power consumption, and reliability, making it an excellent choice for designers looking to implement high-performance memory solutions in their applications. Its combination of lasting performance and advanced features secures its place in both current and future electronic designs.
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