Cypress CY7C1336H manual Switching Characteristics Over the Operating Range 10

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PRELIMINARY

 

 

 

CY7C1336H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Characteristics Over the Operating Range [10, 11]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

133 MHz

100 MHz

 

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

 

t

 

V (Typical) to the First Access[12]

 

1

 

1

 

ms

 

POWER

 

DD

 

 

 

 

 

 

 

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

 

7.5

 

10

 

ns

 

tCH

 

Clock HIGH

 

2.5

 

4.0

 

ns

 

tCL

 

Clock LOW

 

2.5

 

4.0

 

ns

 

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCDV

 

Data Output Valid after CLK Rise

 

 

6.5

 

8.0

ns

 

tDOH

 

Data Output Hold after CLK Rise

 

2.0

 

2.0

 

ns

 

tCLZ

 

Clock to Low-Z[13, 14, 15]

 

0

 

0

 

ns

 

tCHZ

 

Clock to High-Z[13, 14, 15]

 

 

3.5

 

3.5

ns

 

tOEV

 

 

 

LOW to Output Valid

 

 

3.5

 

3.5

ns

 

OE

 

 

 

tOELZ

 

 

 

LOW to Output Low-Z[13, 14, 15]

 

0

 

0

 

ns

 

OE

 

 

 

tOEHZ

 

 

 

HIGH to Output High-Z[13, 14, 15]

 

 

3.5

 

3.5

ns

 

OE

 

 

 

Set-up Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Set-up before CLK Rise

 

1.5

 

2.0

 

ns

 

tADS

 

 

 

 

 

 

 

 

 

 

Set-up before CLK Rise

 

1.5

 

2.0

 

ns

 

ADSP,

ADSC

 

 

 

tADVS

 

 

 

 

 

Set-up before CLK Rise

 

1.5

 

2.0

 

ns

 

ADV

 

 

 

tWES

 

 

 

 

 

 

 

 

 

 

 

[A:D] Set-up before CLK Rise

 

1.5

 

2.0

 

ns

 

GW,

BWE,

BW

 

 

 

tDS

 

Data Input Set-up before CLK Rise

 

1.5

 

2.0

 

ns

 

tCES

 

Chip Enable Set-up

 

1.5

 

2.0

 

ns

 

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold after CLK Rise

 

0.5

 

0.5

 

ns

 

tADH

 

 

 

 

 

 

 

 

 

 

Hold after CLK Rise

 

0.5

 

0.5

 

ns

 

ADSP,

ADSC

 

 

 

tWEH

 

 

 

 

 

 

 

 

 

 

 

[A:D] Hold after CLK Rise

 

0.5

 

0.5

 

ns

 

GW,

BWE,

BW

 

 

 

tADVH

 

 

 

 

Hold after CLK Rise

 

0.5

 

0.5

 

ns

 

ADV

 

 

 

tDH

 

Data Input Hold after CLK Rise

 

0.5

 

0.5

 

ns

 

tCEH

 

Chip Enable Hold after CLK Rise

 

0.5

 

0.5

 

ns

 

Notes:

10.Timing reference level is 1.5V when VDDQ = 3.3V.

11.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

12.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated.

13.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

14.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

15.This parameter is sampled and not 100% tested.

Document #: 001-00210 Rev. *A

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Contents Logic Block Diagram FeaturesFunctional Description1 Cypress Semiconductor CorporationSelection Guide Pin Configuration15CY7C1336H 133 MHz 100 MHz UnitPin Definitions Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description UsedTruth Table for Read/Write 2 FunctionBWE Operating Range Maximum RatingsAmbient RangeThermal Resistance9 Capacitance9AC Test Loads and Waveforms Parameter Description Test Conditions Tqfp UnitSwitching Characteristics Over the Operating Range 10 Read Cycle Timing16 Timing DiagramsCLK Write Cycle Timing16Adsc ADVAdsp Adsc Read/Write Timing16, 18Address Burst ReadZZ Mode Timing20 Package Diagram Ordering InformationPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document HistoryREV ECN no

CY7C1336H specifications

The Cypress CY7C1336H is a high-performance static random-access memory (SRAM) device that has gained recognition for its outstanding speed and reliability. This component is widely used in various high-performance applications including networking, telecommunications, and industrial control systems, where fast data storage and retrieval are critical.

One of the main features of the CY7C1336H is its high-speed operation, offering access times of as low as 10 nanoseconds. This makes it ideal for applications that require quick response times and efficient processing. The device operates with a supply voltage of 2.5V, which not only helps in reducing power consumption but also enables its use in newer low-voltage systems.

The CY7C1336H boasts a capacity of 1 megabit, organized in a configuration of 128K words by 8 bits. This allows it to store a significant amount of data while maintaining a compact footprint. In addition to its size, the device supports a burst mode, which enhances its efficiency in handling data transfer operations. This feature is particularly useful in applications requiring continuous data streaming, such as video processing or high-speed networking.

The memory technology employed in the CY7C1336H is known for its robustness and durability. Unlike DRAM, SRAM does not require periodic refreshing, which simplifies system design and improves overall performance. The device also features fast output enable and chip enable options, providing greater flexibility in controlling memory access and improving overall system response time.

In terms of packaging, the CY7C1336H is available in various forms including 32-pin SOJ and 44-pin TSOP packages, catering to diverse design requirements. Its compact packaging and low thermal characteristics make it suitable for space-constrained applications.

Another noteworthy characteristic of this SRAM is its inherent data integrity and reliability. With features such as on-chip parity generation and error checking capabilities, the CY7C1336H ensures that the data stored remains accurate and consistent over time.

Overall, the Cypress CY7C1336H delivers a blend of high speed, low power consumption, and reliability, making it an excellent choice for designers looking to implement high-performance memory solutions in their applications. Its combination of lasting performance and advanced features secures its place in both current and future electronic designs.
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