Cypress CY7C1339G manual 250 200 166 133 Parameter Description Unit Min Max, Clock, Output Times

CY7C1339G

Switching Characteristics Over the Operating Range[12, 13, 14, 15, 16, 17]

											–250		–200		–166		–133
Parameter										Description									Unit
											Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max.
tPOWER	VDD(Typical) to the first Access[12]										1		1		1		1		ms
Clock
tCYC	Clock Cycle Time										4.0		5.0		6.0		7.5		ns
tCH	Clock HIGH										1.7		2.0		2.5		3.0		ns
tCL	Clock LOW										1.7		2.0		2.5		3.0		ns
Output Times
tCO	Data Output Valid After CLK Rise											2.6		2.8		3.5		4.0	ns
tDOH	Data Output Hold After CLK Rise										1.0		1.0		1.5		1.5		ns
tCLZ	Clock to Low-Z[13, 14, 15]										0		0		0		0		ns
tCHZ	Clock to High-Z[13, 14, 15]											2.6		2.8		3.5		4.0	ns
tOEV		LOW to Output Valid										2.6		2.8		3.5		4.0	ns
	OE
t		LOW to Output Low-Z[13, 14, 15]									0		0		0		0		ns
	OE
OELZ
tOEHZ		HIGH to Output High-Z[13, 14, 15]										2.6		2.8		3.5		4.0	ns
	OE
Set-up Times
tAS	Address Set-up Before CLK Rise										1.2		1.2		1.5		1.5		ns
tADS									Set-up Before CLK Rise		1.2		1.2		1.5		1.5		ns
	ADSC,					ADSP
tADVS				Set-up Before CLK Rise							1.2		1.2		1.5		1.5		ns
	ADV
tWES										X Set-up Before CLK Rise	1.2		1.2		1.5		1.5		ns
	GW,			BWE,			BW
tDS	Data Input Set-up Before CLK Rise										1.2		1.2		1.5		1.5		ns
tCES	Chip Enable Set-Up Before CLK Rise										1.2		1.2		1.5		1.5		ns
Hold Times
tAH	Address Hold After CLK Rise										0.3		0.5		0.5		0.5		ns
tADH								Hold After CLK Rise			0.3		0.5		0.5		0.5		ns
	ADSP,				ADSC
tADVH			Hold After CLK Rise								0.3		0.5		0.5		0.5		ns
	ADV
tWEH										X Hold After CLK Rise	0.3		0.5		0.5		0.5		ns
	GW,			BWE,			BW
tDH	Data Input Hold After CLK Rise										0.3		0.5		0.5		0.5		ns
tCEH	Chip Enable Hold After CLK Rise										0.3		0.5		0.5		0.5		ns

Notes:

12.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated.

13.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

14.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

15.This parameter is sampled and not 100% tested.

16.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05520 Rev. *F Page 10 of 18

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