Cypress CY7C1352G manual Maximum Ratings, Operating Range, Ambient Range, Gnd ≤ V I ≤ V Ddq

CY7C1352G

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature		−65°C to +150°C
Ambient Temperature with
Power Applied		−55°C to +125°C
Supply Voltage on VDD Relative to GND		−0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND		−0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state	−0.5V to VDDQ + 0.5V

Electrical Characteristics Over the Operating Range[9, 10]

DC Input Voltage		−0.5V to VDD + 0.5V
Current into Outputs (LOW)			20 mA
Static Discharge Voltage			> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current			> 200 mA
Operating Range
	Ambient
Range	Temperature (TA)	VDD	VDDQ
Commercial	0°C to +70°C	3.3V –5%	2.5V –5%
		+10%	to VDD
Industrial	–40°C to +85°C

Parameter		Description	Test Conditions		Min.	Max.	Unit
VDD		Power Supply Voltage			3.135	3.6	V
VDDQ		I/O Supply Voltage			2.375	VDD	V
VOH		Output HIGH Voltage	for 3.3V I/O, IOH = –4.0 mA		2.4		V
			for 2.5V I/O, IOH = –1.0 mA		2.0		V
VOL		Output LOW Voltage	for 3.3V I/O, IOL = 8.0 mA			0.4	V
			for 2.5V I/O, IOL = 1.0 mA			0.4	V
V	IH	Input HIGH Voltage[9]	for 3.3V I/O		2.0	V + 0.3V	V
						DD
			for 2.5V I/O		1.7	VDD + 0.3V	V
VIL		Input LOW Voltage[9]	for 3.3V I/O		–0.3	0.8	V
			for 2.5V I/O		–0.3	0.7	V
IX		Input Leakage Current	GND ≤ VI ≤ VDDQ		−5	5	µA
		except ZZ and MODE
		Input Current of MODE	Input = VSS		−30		µA
			Input = VDD			5	µA
		Input Current of ZZ	Input = VSS		−5		µA
			Input = VDD			30	µA
IOZ		Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		−5	5	µA
IDD		VDD Operating Supply	VDD = Max., IOUT = 0 mA,	4-ns cycle, 250 MHz		325	mA
		Current	f = fMAX = 1/tCYC
				5-ns cycle, 200 MHz		265	mA
				6-ns cycle, 166 MHz		240	mA
				7.5-ns cycle,133 MHz		225	mA
ISB1		Automatic CE	VDD = Max, Device Deselected,	4-ns cycle, 250 MHz		120	mA
		Power-Down	VIN ≥ VIH or VIN ≤ VIL
				5-ns cycle, 200 MHz		110	mA
		Current—TTL Inputs	f = fMAX = 1/tCYC
				6-ns cycle, 166 MHz		100	mA
				7.5-ns cycle,133 MHz		90	mA
ISB2		Automatic CE	VDD = Max, Device Deselected,	All speeds		40	mA
		Power-down	VIN ≤ 0.3V or
		Current—CMOS Inputs	VIN > VDDQ – 0.3V, f = 0
ISB3		Automatic CE	VDD = Max, Device Deselected,	4-ns cycle, 250 MHz		105	mA
		Power-down	or VIN ≤ 0.3V or
				5-ns cycle, 200 MHz		95	mA
		Current—CMOS Inputs	VIN > VDDQ – 0.3V
			f = fMAX = 1/tCYC	6-ns cycle, 166 MHz		85	mA
				7.5-ns cycle,133 MHz		75	mA

Notes:

9.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).

10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05514 Rev. *D Page 6 of 12

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