Cypress CY7C1352G manual Features, Functional Description1, Logic Block Diagram

CY7C1352G

4-Mbit (256K x 18) Pipelined SRAM with NoBL™ Architecture

Features

•Pin compatible and functionally equivalent to ZBT™ devices

•Internally self-timed output buffer control to eliminate the need to use OE

•Byte Write capability

•256K x 18 common I/O architecture

•3.3V core power supply (VDD)

•2.5V/3.3V I/O power supply (VDDQ)

•Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

•Clock Enable (CEN) pin to suspend operation

•Synchronous self-timed writes

•Asynchronous output enable (OE)

•Available in lead-free 100-Pin TQFP package

•Burst Capability—linear or interleaved burst order

•ZZ” Sleep Mode Option and Stop Clock option

Functional Description[1]

The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consec- utive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.6 ns (250-MHz device).

Write operations are controlled by the two Byte Write Select (BW[A:B]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

ADDRESS

REGISTER 0

A1

D1

Q1 A1'

MODE

A0

D0 BURST Q0 A0'

ADV/LD

LOGIC

CLK

C

C

CEN

WRITE ADDRESS

WRITE ADDRESS

REGISTER 1

REGISTER 2

O

O

U

U

T

T

ADV/LD

S

P

D

P

E

U

A

U

WRITE REGISTRY

N

T

T

T

MEMORY

S

R

A

B

BWA

AND DATA COHERENCY

WRITE

E

DQs

ARRAY

E

S

U

CONTROL LOGIC

DRIVERS

A

G

DQPA

T

F

BWB

M

I

E

F

DQPB

P

S

E

E

S

T

R

R

E

I

S

WE

R

N

S

G

E

E

INPUT

E

INPUT

E

REGISTER 1

REGISTER 0

OE

READ LOGIC

CE1

CE2

CE3

ZZ

Sleep

Control

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05514 Rev. *D		Revised July 4, 2006

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