Cypress CY14B108K AC Switching Characteristics, Switching Waveforms, Parameters Sram Read Cycle

Page 18

				PRELIMINARY		CY14B108K, CY14B108M
						CY14B108K, CY14B108M


AC Switching Characteristics

Parameters				Description	20 ns		25 ns		45 ns		Unit
Cypress	Alt			Description	Min	Max	Min	Max	Min	Max	Unit
Parameters	Parameters				Min	Max	Min	Max	Min	Max
Parameters	Parameters
SRAM Read Cycle
tACE	tACS			Chip Enable Access Time		20		25		45	ns
tRC [15]	tRC			Read Cycle Time	20		25		45		ns
tAA [16]	tAA			Address Access Time		20		25		45	ns
tDOE	tOE			Output Enable to Data Valid		10		12		20	ns
tOHA[16]	tOH			Output Hold After Address Change	3		3		3		ns
tLZCE [13, 17]	tLZ			Chip Enable to Output Active	3		3		3		ns
tHZCE [13, 17]	tHZ			Chip Disable to Output Inactive		8		10		15	ns
tLZOE [13, 17]	tOLZ			Output Enable to Output Active	0		0		0		ns
tHZOE [13, 17]	tOHZ			Output Disable to Output Inactive		8		10		15	ns
tPU [13]	tPA			Chip Enable to Power Active	0		0		0		ns
tPD [13]	tPS			Chip Disable to Power Standby		20		25		45	ns
tDBE	-			Byte Enable to Data Valid		10		12		20	ns
tLZBE[13]	-			Byte Enable to Output Active	0		0		0		ns
tHZBE[13]	-			Byte Disable to Output Inactive		8		10		15	ns
SRAM Write Cycle
tWC	tWC			Write Cycle Time	20		25		45		ns
tPWE	tWP			Write Pulse Width	15		20		30		ns
tSCE	tCW			Chip Enable To End of Write	15		20		30		ns
tSD	tDW			Data Setup to End of Write	8		10		15		ns
tHD	tDH			Data Hold After End of Write	0		0		0		ns
tAW	tAW			Address Setup to End of Write	15		20		30		ns
tSA	tAS			Address Setup to Start of Write	0		0		0		ns
tHA	tWR			Address Hold After End of Write	0		0		0		ns
tHZWE [13, 17,18]	tWZ			Write Enable to Output Disable		8		10		15	ns
tLZWE [13, 17]	tOW			Output Active after End of Write	3		3		3		ns
tBW	-			Byte Enable to End of Write	15		20		30		ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled[15, 16, 19]

	tRC
Address	Address Valid
	tAA
Data Output	Previous Data Valid
	tOHA

Notes

15.WE must be HIGH during SRAM read cycles.

16.Device is continuously selected with CE, OE and BHE / BLE LOW.

17.Measured ±200 mV from steady state output voltage.

18.If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.

19.HSB must remain HIGH during Read and Write cycles.

Output Data Valid

Document #: 001-47378 Rev. **

Page 18 of 29

[+] Feedback

Image 18

Contents Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor CorporationPinouts Sram Write Device OperationSram Read AutoStore OperationSoftware Recall Hardware Recall Power UpHardware Store HSB Operation Software StorePreventing AutoStore Mode SelectionA15 A05 Mode Power StoreData Protection Best Practices Noise ConsiderationsReal Time Clock Operation Alarm Watchdog TimerCalibrating the Clock Interrupts Power MonitorInterrupt Register Flags RegisterPFE Power Fail Enable WDF Watchdog Timer FlagPF Power Fail Flag AF Alarm FlagOscen WDSWDF Oscf 0xFFFF9 0x7FFF9 Time Keeping Seconds For the register is 0 toWrite only. Reading it always returns a 0xFFFF5 0x7FFF5 Alarm DayTime-base 0xFFFF6 0x7FFF6 Interrupt Status/ControlWatchdog 0xFFFF2 0x7FFF2 Alarm SecondsCenturies 0xFFFF0 0x7FFF0 Flags This condition and write 0 to clear this flagMaximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsRTC Battery Pin Voltage RTC Backup CurrentHot Temperature 85 oC RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to StartParameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write CycleAddress Address Valid Data Output High Impedance Output Data ValidStandby Active Data Input Input Data ValidNot applicable for RTC register writes Data Input Data OutputInput Data Valid High Impedance Data Input Input Data Valid High Impedance Data OutputAutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled Store and Recall Cycle Description 20 ns 25 ns 45 ns Unit Min To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthInputs and Outputs Mode Power For x8 ConfigurationFor x16 Configuration Truth Table For Sram OperationsPart Numbering Nomenclature CY14 B 108 K ZS P 20 X C T ZS TsopNvsram Ordering Information Package Diagrams Pin Tsop II51-85160 New Data Sheet Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History