Cypress CY14B108K, CY14B108M manual Data Protection Best Practices, Noise Considerations

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PRELIMINARY

CY14B108K, CY14B108M

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Protection

 

Best Practices

 

 

The CY14B108K/CY14B108M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B108K/CY14B108M is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power up or brown out conditions.

Noise Considerations

Refer to CY application note AN1064.

nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:

■The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufac- turing test to ensure these system routines work consistently.

■Power up boot firmware routines should rewrite the nvSRAM into the desired state (for example, autostore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines.

■The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this maximum VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period.

Document #: 001-47378 Rev. **

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Contents Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor CorporationPinouts Sram Write Device OperationSram Read AutoStore OperationSoftware Recall Hardware Recall Power UpHardware Store HSB Operation Software StorePreventing AutoStore Mode SelectionA15 A05 Mode Power StoreData Protection Best Practices Noise ConsiderationsReal Time Clock Operation Alarm Watchdog TimerCalibrating the Clock Interrupts Power MonitorInterrupt Register Flags RegisterPFE Power Fail Enable WDF Watchdog Timer FlagPF Power Fail Flag AF Alarm FlagOscen WDSWDF Oscf 0xFFFF9 0x7FFF9 Time Keeping Seconds For the register is 0 toWrite only. Reading it always returns a 0xFFFF5 0x7FFF5 Alarm DayTime-base 0xFFFF6 0x7FFF6 Interrupt Status/ControlWatchdog 0xFFFF2 0x7FFF2 Alarm SecondsCenturies 0xFFFF0 0x7FFF0 Flags This condition and write 0 to clear this flagMaximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsRTC Battery Pin Voltage RTC Backup CurrentHot Temperature 85 oC RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to StartParameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write CycleAddress Address Valid Data Output High Impedance Output Data ValidStandby Active Data Input Input Data ValidNot applicable for RTC register writes Data Input Data OutputInput Data Valid High Impedance Data Input Input Data Valid High Impedance Data OutputAutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled Store and Recall Cycle Description 20 ns 25 ns 45 ns Unit Min To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthInputs and Outputs Mode Power For x8 ConfigurationFor x16 Configuration Truth Table For Sram OperationsPart Numbering Nomenclature CY14 B 108 K ZS P 20 X C T ZS TsopNvsram Ordering Information Package Diagrams Pin Tsop II51-85160 New Data Sheet Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History
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