Cypress CY14B108M, CY14B108K manual AutoStore/Power Up Recall

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PRELIMINARY

CY14B108K, CY14B108M

AutoStore/Power Up RECALL

Parameters

Description

20 ns

25 ns

45 ns

Unit

Min

Max

Min

Max

Min

Max

t

[22]

Power Up RECALL Duration

20

20

20

ms

HRECALL

tSTORE [23]

STORE Cycle Duration

8

8

8

ms

tDELAY [24]

Time Allowed to Complete SRAM Cycle

20

25

25

ns

VSWITCH

Low Voltage Trigger Level

2.65

2.65

2.65

V

tVCCRISE

VCC Rise Time

150

150

150

μs

VHDIS[13]

Output Driver Disable Voltage

1.9

1.9

1.9

V

HSB

tLZHSB

To Output Active Time

5

5

5

μs

HSB

tHHHD

High Active Time

500

500

500

ns

HSB

Switching Waveforms

Figure 12. AutoStore or Power Up RECALL[25]

VSWITCH
VHDIS
VVCCRISE	Note23	t	Note23	t
		STORE		STORE
	tHHHD		tHHHD	Note26
	tHHHD		tHHHD
HSB OUT			tDELAY
			tDELAY
	tLZHSB		t
Autostore			LZHSB
Autostore
	tDELAY
POWER-
UP
RECALL	tHRECALL		tHRECALL
			tHRECALL

Read & Write

Inhibited

(RWI)

POWER-UP Read & Write	BROWN	POWER-UP	Read & Write	POWER
RECALL	OUT	RECALL		DOWN
	Autostore			Autostore

Notes

22.tHRECALL starts from the time VCC rises above VSWITCH.

23.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

24.On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.

25.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.

26.HSB pin is driven HIGH to VCC only by internal 100 kΩ resistor, HSB driver is disabled.

Document #: 001-47378 Rev. **

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Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationPinouts Sram Read Device OperationSram Write AutoStore OperationHardware Store HSB Operation Hardware Recall Power UpSoftware Recall Software StoreA15 A05 Mode Power Mode SelectionPreventing AutoStore StoreNoise Considerations Data Protection Best PracticesReal Time Clock Operation Alarm Watchdog TimerCalibrating the Clock Interrupt Register Power MonitorInterrupts Flags RegisterPF Power Fail Flag WDF Watchdog Timer FlagPFE Power Fail Enable AF Alarm FlagOscen WDSWDF Oscf For the register is 0 to 0xFFFF9 0x7FFF9 Time Keeping SecondsTime-base 0xFFFF5 0x7FFF5 Alarm DayWrite only. Reading it always returns a 0xFFFF6 0x7FFF6 Interrupt Status/ControlCenturies 0xFFFF0 0x7FFF0 Flags 0xFFFF2 0x7FFF2 Alarm SecondsWatchdog This condition and write 0 to clear this flagRange Ambient Temperature DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsHot Temperature 85 oC RTC Backup CurrentRTC Battery Pin Voltage RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to StartSwitching Waveforms AC Switching CharacteristicsParameters Sram Read Cycle Sram Write CycleStandby Active Data Output High Impedance Output Data ValidAddress Address Valid Data Input Input Data ValidInput Data Valid High Impedance Data Input Data OutputNot applicable for RTC register writes Data Input Input Data Valid High Impedance Data OutputParameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallSoftware Controlled Store and Recall Cycle Hardware Store Cycle To Output Active Time when write latch not setDescription 20 ns 25 ns 45 ns Unit Min Hardware Store Pulse WidthFor x16 Configuration For x8 ConfigurationInputs and Outputs Mode Power Truth Table For Sram OperationsPart Numbering Nomenclature CY14 B 108 K ZS P 20 X C T ZS TsopNvsram Ordering Information Pin Tsop II Package Diagrams51-85160 Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationNew Data Sheet Document History