Cypress CY14E256L manual Features, Functional Description

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CY14E256L

256 Kbit (32K x 8) nvSRAM

Features

25 ns, 35 ns, and 45 ns access times

Pin compatible with STK14C88

Hands off automatic STORE on power down with external 68 µF capacitor

STORE to QuantumTrap™ nonvolatile elements is initiated by software, hardware, or AutoStore™ on power down

RECALL to SRAM initiated by software or power up

Unlimited READ, WRITE, and RECALL cycles

1,000,000 STORE cycles to QuantumTrap

100 year data retention to QuantumTrap

Single 5V+10% operation

Commercial and industrial temperature

32-pin SOIC and CDIP (300 mil) packages

RoHS compliance

Functional Description

The Cypress CY14E256L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin.

Logic Block Diagram

 

 

 

VCC

VCAP

 

 

 

 

 

Quantum Trap

 

 

 

 

 

 

 

 

 

 

 

 

 

 

512 X 512

 

POWER

 

 

A5

 

 

 

 

 

 

 

 

STORE

 

CONTROL

 

 

A6

DECODER

 

 

 

 

 

 

 

 

 

 

 

A7

 

RECALL

 

 

 

 

 

A8

 

 

STORE/

 

 

A9

STATIC RAM

 

RECALL

HSB

 

 

ARRAY

 

 

A11

 

 

CONTROL

 

 

ROW

 

512 X 512

 

 

 

 

 

A12

 

 

 

 

 

 

 

 

 

 

 

 

 

A13

 

 

 

 

 

 

 

A14

 

 

 

 

 

SOFTWARE

 

A13 - A0

 

 

 

 

 

 

DETECT

 

DQ0

 

COLUMN I/O

 

 

 

 

 

DQ1

BUFFERS

COLUMN DEC

 

 

 

 

 

DQ2

 

 

 

 

 

 

 

 

 

 

 

 

DQ3

 

 

 

 

 

 

 

DQ4

 

 

 

 

 

 

 

INPUT

 

 

 

 

 

 

 

DQ5

A0 A1 A2 A3 A4 A10

 

 

 

 

 

DQ6

 

 

 

 

 

 

 

DQ7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

WE

Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document Number: 001-06968 Rev. *F

 

 

 

 

Revised January 30, 2009

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Contents Functional Description FeaturesPin Definitions Pin ConfigurationsDevice Operation AutoStore Inhibit modeSram Read Sram WriteHardware Store HSB Operation Hardware Recall Power UpSoftware Store Software RecallData Protection Low Average Active PowerNoise Considerations Hardware ProtectA13-A0 Mode Power Hardware Mode SelectionBest Practices Range Ambient Temperature DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsMin Max ParameterData Setup to End of Write Chip Enable To End of WriteAddress Setup to End of Write Address Setup to Start of WriteParameter Alt Description CY14E256L Unit Min Max AutoStore or Power Up RecallAlt Description 25 ns 35 ns 45 ns Unit Min Max Software Controlled STORE/RECALL CycleHardware Store High to Inhibit Off 700 Hardware Store CycleHardware Store Pulse Width Hardware Store Low to Store Busy 300Ordering Information Pin 300 Mil Soic Package DiagramPin 300 Mil Cdip Document History USB Sales, Solutions, and Legal Information