Cypress CY14E256L manual Pin Configurations, Pin Definitions

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CY14E256L

Pin Configurations

Figure 1. Pin Diagram: 32-Pin SOIC/DIP

Pin Definitions

Pin Name

Alt

IO Type

 

 

Description

A0–A14

 

 

 

 

 

 

 

Input

Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.

DQ0-DQ7

 

 

 

 

 

 

 

Input or Output

Bidirectional Data IO Lines. Used as input or output lines depending on operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Write Enable Input, Active LOW. When the chip is enabled and

 

is LOW, data on the IO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

WE

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pins is written to the specific address location.

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

 

 

 

CE

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Output Enable, Active LOW. The active LOW

 

input enables the data output buffers during

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

OE

 

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

 

VSS

 

 

 

 

 

 

 

Ground

Ground for the Device. The device is connected to ground of the system.

 

VCC

 

 

 

 

 

 

 

Power Supply

Power Supply Inputs to the Device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input or Output

Hardware Store Busy

(HSB)

. When LOW, this output indicates a Hardware Store is in progress.

 

HSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pull up resistor keeps this pin high if not connected (connection optional).

VCAP

 

 

 

 

 

 

 

Power Supply

AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to nonvolatile elements.

Document Number: 001-06968 Rev. *F

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Contents Features Functional DescriptionPin Configurations Pin DefinitionsSram Read AutoStore Inhibit modeDevice Operation Sram WriteSoftware Store Hardware Recall Power UpHardware Store HSB Operation Software RecallNoise Considerations Low Average Active PowerData Protection Hardware ProtectBest Practices Hardware Mode SelectionA13-A0 Mode Power Maximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsMin Max AC Switching CharacteristicsSwitching Waveforms ParameterAddress Setup to End of Write Chip Enable To End of WriteData Setup to End of Write Address Setup to Start of WriteAutoStore or Power Up Recall Parameter Alt Description CY14E256L Unit Min MaxSoftware Controlled STORE/RECALL Cycle Alt Description 25 ns 35 ns 45 ns Unit Min MaxHardware Store Pulse Width Hardware Store CycleHardware Store High to Inhibit Off 700 Hardware Store Low to Store Busy 300Ordering Information Package Diagram Pin 300 Mil SoicPin 300 Mil Cdip Document History Sales, Solutions, and Legal Information USB
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