|
|
For addition, the | |
| zero bit position, represents a carry. This bit gets set |
| (C=1) to indicate a carry, and is reset (C=0) if there is |
| no carry. |
| For subtraction, the C bit is set (C=1) to indicate a |
| borrow and is reset (C=0) to indicate there was no borrow. |
Overflow: | The V bit (bit 1) of the condition code register is set |
| (V=1) when two's complement overflow results from an |
| arithmetic operation, and is reset (V=O) if two's |
| complement overflow does not occur. |
Zero: | The Z bit (bit 2) of the condition code register is set |
| (Z=1) if the result of an arithmetic operation is zero, and |
| is reset (Z=0) if the result is not zero. |
Negative: | The N bit (bit 3) of the condition code register is set |
| (N=1) if bit 7 of an arithmetic operation is set (equal to |
| 1). This indicates that the two's complement number, |
| represented by the bit pattern of the result, is negative. |
| The N bit is reset (N=0) if bit 7 of the arithmetic result |
| is equal to 0. |
Interrupt Mask: If this I bit (bit 4) is set (I=1), the MPU cannot respond
| to an interrupt request from any peripheral device. |
The half carry bit H (bit 5) of the condition code register | |
| is set (H=1) during execution of any of the instructions |
| ABA,ADC, or ADD, if there is a carry from bit position 3 to |
| bit position 4. The half carry is reset (H=0) during these |
| operations, if there is no carry from bit position 4. |