MPU-9
Counter, Accumulators, and Condition Code Register are stored away on the stack. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations n-6 and n-7 where n is the highest ROM address. An address loaded at these locations causes the MPU to branch to an interrupt routine in memory.
5.Phase One (Øl)& Phase (Ø2)Clocks:
These two pins are used or a two phase non-overlapping clock that runs at the V DD voltage level.
These clocks run at a rate up to 1 megahertz.
6. Restart (RES):
RESTART (RES)--This input is used to start the MPU from a power down condition, resulting from a power failure or an initial start-up of the processor. If a positive edge is detected on the input, this will signal the MPU to begin the restart sequence. This will restart the MPU and start execution of a routine to initialize the processor. All the higher order address lines will be forced high. For the restart, the last 2 memory locations in the last ROM (n&n-1) will be accessed, whereby an address is stored which is the address to be loaded in the program counter which tells the processor where program execution is to begin.
7.NON-MASKABLE INTERRUPT(NMI):
This input requests that a nonmask-interrupt sequence be generated within the processor. As with the Interrupt