Motorola M6800 Aba, Ins, Adc, Inx, Add, Jmp, Asl, Jsr, Asr, Lda, Lds, Bcc, Ldx, Bcs, Lsr, Beq

Page 12

MPU-12

Microprocessor Instruction Set -- Alphabetic Sequence

ABA

Add Accumulators

INS

Increment Stack Pointer

ADC

Add with Carry

INX

Increment Index Register

ADD

Add

 

 

AND

Logical And

JMP

Jump

ASL

Arithmetic Shift Left

JSR

Jump to Subroutine

ASR

Arithmetic Shift Right

LDA

Load Accumulator

 

 

LDS

Load Stack Pointer

BCC

Branch if Carry Clear

LDX

Load Index Register

BCS

Branch if Carry Set

LSR

Logical Shift Right

BEQ

Branch if Equal to Zero

 

 

BGE

Branch if Greater or Equal

NEG

Negate

 

Zero

 

 

BGT

Branch if Greater than Zero

NOP

No Operation

BHI

Branch if Higher

 

 

BIT

Bit Test

ORA

Inclusive OR Accumulator

BLE

Branch if Less or Equal

PSH

Push Data

BLS

Branch if Lower of Same

PUL

Pull Data

BLT

Branch if Less than Zero

ROL

Rotate Left

BMI

Branch if Minus

ROR

Rotate Right

BNE

Branch if Not Equal to Zero

RTI

Return from Interrupt

BPL

Branch if Plus

RTS

Return from Subroutine

BRA

Branch Always

 

 

BSR

Branch to Subroutine

SBA

Subtract Accumulators

BVC

Branch if Overflow Clear

SBC

Subtract with Carry

BVS

Branch if Overflow Set

SEC

Set Carry

 

 

SEI

Set Interrupt Mask

CBA

Compare Accumulators

SEV

Set Overflow

CLC

Clear Carry

STA

Store Accumulator

CLI

Clear Interrupt Mask

STS

Store Stack Register

CLR

Clear

STX

Store Index Register

CLV

Clear Overflow

SUB

Subtract

CMP

Compare

SWI

Software Interrupt

COM

Complement

 

 

CPX

Compare Index Register

TAB

Transfer Accumulators

 

 

TAP

Transfer Accumulators to

 

 

 

Condition Code Reg.

DAA

Decimal Adjust

TBA

Transfer Accumulators

DEC

Decrement

TPA

Transfer Condition Code

 

 

 

Reg. to Accumulator

DES

Decrement Stack Pointer

TST

Test

DEX

Decrement Index Register

TSX

Transfer Stack Pointer

 

 

 

to Index Register

FOR

Exclusive OR

TXS

Transfer Index Register

 

 

 

to Stack Pointer

INC

Increment

WAI

Wait for Interrupt

Image 12
Contents MPU-1 Introduction MPU-2 MPU-3 MPU-4 MPU-5 BIT N0 Function MPU-7 Data BUS Enabledbe MPU-8READ/WRITE R/W Valid Memory AddressvmaMPU-9 NON-MASKABLE InterruptnmiBUS Available BA THREE-STATE Control TSC Address BUS AO/A15ABA INSADC INXPage MPU-14 Summary of MPU Operation Reset Sequence IRQ Sequence NMI Sequence RTI ExecutionSWI Instruction Page Page Page Page Page Page Page Page