Maxtor 54098U8, 51024U2, 52049U4, 51536U3, 53073U6 specifications Ultra DMA Timing, Mode MIN MAX

Page 29

AT INTERFACE DESCRIPTION

Ultra DMA Timing

TIMING PARAMETERS (all times in nanoseconds)

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

Cycle Time (from STROBE edge to STROBE edge)

112

 

73

 

54

 

39

 

25

 

t2CYC

Two cycle time (from rising edge to next rising edge or

230

 

154

 

115

 

86

 

57

 

 

from falling edge to next falling edge of STROBE)

 

 

 

 

 

 

 

 

 

 

tDS

Data setup time (at recipient)

15

 

10

 

7

 

7

 

5

 

tDH

Data hold time (at recipient)

5

 

5

 

5

 

5

 

5

 

tDVS

Data valid setup time at sender (time from data bus being

70

 

48

 

30

 

20

 

6

 

 

valid until STROBE edge)

 

 

 

 

 

 

 

 

 

 

tDVH

Data valid hold time at sender (time from STROBE edge

6

 

6

 

6

 

6

 

6

 

 

until data may go invalid)

 

 

 

 

 

 

 

 

 

 

tFS

First STROBE (time for device to send first STROBE)

0

230

0

200

0

170

0

130

0

120

tLI

Limited interlock time (time allowed between an action by

0

150

0

150

0

150

0

100

0

100

 

one agent, either host or device, and the following action

 

by the other agent)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tMLI

Interlock time with minimum

20

 

20

 

20

 

20

 

20

 

tUI

Unlimited interlock time

0

 

0

 

0

 

0

 

0

 

tAZ

Maximum time allowed for outputs to release

 

10

 

10

 

10

 

10

 

10

tZAH

Minimum delay time required for output drivers turning on

20

 

20

 

20

 

20

 

20

 

tZAD

(from released state)

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

tENV

Envelope time (all control signal transitions are within the

20

70

20

70

20

70

20

55

20

55

 

DMACK envelope by this much time)

 

 

 

 

 

 

 

 

 

 

tSR

STROBE to DMARDY (response time to ensure the

 

50

 

30

 

20

 

NA

 

NA

 

synchronous pause case when the recipient is pausing)

 

 

 

 

 

 

 

 

 

 

tRFS

Ready-to-final-STROBE time (no more STROBE edges may

 

75

 

70

 

60

 

60

 

60

 

be sent this long after receiving DMARDY- negation)

 

 

 

 

 

 

 

 

 

 

tRP

Ready-to-pause time (time until a recipient may assume

160

 

125

 

100

 

100

 

100

 

 

that the sender has paused after negation of DMARDY-)

 

 

 

 

 

 

 

 

 

 

tIORDYZ

Pull-up time before allowing IORDY to be released

 

20

 

20

 

20

 

20

 

20

tZIORDY

Minimum time device shall wait before driving IORDY

0

 

0

 

0

 

0

 

0

 

tACK

Setup and hold times before assertion and negation of

20

 

20

 

20

 

20

 

20

 

 

DMACK-

 

 

 

 

 

 

 

 

 

 

tSS

Time from STROBE edge to STOP assertion when the

50

 

50

 

50

 

50

 

50

 

 

sender is stopping

 

 

 

 

 

 

 

 

 

 

DMARQ

 

(device)

 

tUI

 

DMACK-

 

(host)

 

tACK

tENV

STOP

 

(host)

 

tACK

tENV

HDMARDY-

 

(host)

 

tZIORDY

 

DSTROBE

 

(device)

 

tAZ

 

DD(15:0)

 

tACK

 

DA0, DA1, DA2,

 

CS0-, CS1-

 

tFS

tZAD

 

tFS

 

tZAD

 

tVDS

tDVH

Figure 5 - 4

Initiating an Ultra DMA Data In Burst

5 – 5

Image 29
Contents DiamondMax Plus U T I O N Before You BeginContents Diamondmax Plus 40 Product Manual Product SpecificationsHandling and Installation Host Software Interface Interface CommandsAT Interface Description Glossary Service and SupportFigures MaxtorCorporation IntroductionManualOrganization AbbreviationsDiamondmax Plus 40 Introduction ConventionsProduct Description DiamondMax Plus 40 Key FeaturesFunctional / Interface Product FeaturesModel CYL SPT MAX LBA CapacityCacheManagement MajorHDAComponents Jumper Location / Configuration SubsystemConfigurationJumper Configuration CylinderLimitationJumperDescriptionDriveConfiguration ProductSpecificationsPerformanceSpecifications ModelsandCapacitiesProduct Specifications PhysicalDimensionsmaximumPowerModeDefinitions PowerRequirementsEPA Energy Star Compliance EnvironmentalLimitsParameter Operating NON-OPERATING ReliabilitySpecificationsShock and Vibration EMC/EMI SafetyRegulatoryComplianceElectro-StaticDischargeESD HandlingandInstallationHardDriveHandlingPrecautions UnpackingandInspection InstallationRepacking PhysicalInstallationHook up Before You BeginStart up Set upPIN Signal InterfaceConnectorATInterfaceDescription PinDescriptionSummaryAT Interface Description PIN Name Signal Name Signal DescriptionPin Description Table PIO Timing Timing Parameters ModeDMATiming Timing Parameters Mode 0 Mode 1 ModeUltra DMA Timing Mode MIN MAXSustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst Task File Registers HostSoftwareInterfacePort Read Write Abrt TK0 AmnfBusy Drdy DSC DRQ ERR Contents LBA BitsHost Software Interface LBA DRV HS3 HS2 HS1 HS0CommandRegister Timer Value TIME-OUT Period Command Name Command Code Parameters UsedSummary SDHDS0 Control Diagnostic RegistersIEN Reset and Interrupt Handling InterfaceCommands Interface Commands ReadCommandsRead DMA WriteCommands Write Multiple Value Description SetFeatureCommandsPowerModeCommands Timer Value TIME-OUT Period Word Content Description InitializationCommands15-8 = PIO data transfer mode Interface Commands Word Content Description Initialize Drive Parameters Error Code Description Seek,FormatandDiagnosticCommandsKey Register A.R.T. CommandSetServicePolicy ServiceandSupportNoQuibble Service SupportFrom Dial Service and SupportGlossary Directaccess CorrectableerrorDirectmemoryaccess ErrorcorrectioncodeeccHeaddiskassemblyhda HarderrorExtrapulse FeedbackLandingzoneorlzone PhaselockedlooppllLatebit LatewindowRandomaccessmemoryram PhasemarginReadgatesignal RecoverableerrorStrobeoffsetsignal SofterrorUN-CORRECTABLEERROR Unrecoverableerror

51536U3, 53073U6, 52049U4, 54098U8, 51024U2 specifications

The Maxtor 51024U2, 53073U6, 51536U3, 52049U4, and 54098U8 are part of the celebrated Maxtor family of external hard drives, known for their reliability, performance, and technology innovations. These drives cater to various data storage needs, from casual home use to more demanding business applications.

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