Motherboard Description | SY-7IS2 |
•Upstream accelerated hub architecture interface for access to the MCH
1-6.2 Intel® 815EP MCH Overview
The Intel ® 815EP MCH functions and capabilities include:
•Support Uni-processor system
•64-bit AGTL+ based System Bus Interface at 66/100/133 MHz
•32-bit Host Address Support
•64-bit System Memory Interface with optimized support for SDRAM at 100/133 MHz
•AGP 1X/2X/4X Controller
1-6.3 Host Interface
The host interface of the Intel ® 815EP MCH is optimized to support the Intel ® Pentium III processor and Intel ® Celeron ™ Processor in the FC-PGA package. The Intel ® 815EP MCH implements the host address, control, and data bus interfaces within a single device. The Intel ® 815EP MCH supports a 4-deep in-order queue(i.e., supports pipelining of up to 4 outstanding transaction requests on the host bus). Host bus addresses are decoded by the Intel ® 815EP MCH for accesses to system memory, PCI memory and PCI I/O (via hub interface), PCI configuration space and Graphics memory. The Intel ® 815EP MCH takes advantage of the pipelined addressing capability of the pipelined addressing capability of the processor to improve the overall system performance.
The Intel ® 815EP MCH supports the 370-pin socket processor.
*370-pin socket (PGA370). The PGA370 is a zero insertion force (ZIF) socket that a processor in the FC-PGA package will use to interface with a system board.
1-6.4 System Memory Interface
The Intel ® 815EP MCH integrates a system memory controller that supports a 64-bit 100/133 MHz SDRAM array. The only DRAM type supported is industry standard Synchronous DRAM (SDRAM).
8
