Motherboard Description |
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The AGP interface supports 4x AGP signaling. AGP semantic (PIPE# or SBA[7:0]) cycles to SDRAM are not snooped on the host bus. AGP FRAME# cycles to SDRAM are snooped on the host bus. The MCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. High priority accesses are supported. Only memory writes form the hub interface to AGP are allowed. No transactions from AGP to the hub interface are allowed.
1-6.6 Hub Interface
The hub interface is a private interconnect between the Intel® 815EP MCH and the ICH2.
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