Silicon Image SSD-D32G(I)-4300 manual True IDE PIO Mode Read/Write Access Timing

ELECTRICAL SPECIFICATION SSD-DXXX(I)-4300 DATA SHEET

Table 11: True IDE PIO Mode Read/Write Access Timing

Symbol	Item	Mode 0 Mode 1 Mode 2			Mode 3 Mode 4 Mode 5 Mode 6 Note					Units
t0	Cycle Time (minimum)	600	383	240	180	120	100	80	1	ns
t1	Address Valid to	70	50	30	30	25	15	10	-	ns
	IORD/-IOWR Setup
	(minimum)
t2	-IORD/-IOWR (minimum)	165	125	100	80	70	65	55	1	ns
t2	-IORD/-IOWR (minimum)	290	290	290	80	70	65	55	1	ns
	register (8 bit)
t2i	-IORD/-IOWR Recovery	-	-	-	70	25	25	20	1	ns
	Time (minimum)
t3	-IOWR Data Setup	60	45	30	30	20	20	15	-	ns
	(minimum)
t4	-IOWR Data Hold	30	20	15	10	10	5	5	-	ns
	(minimum)
t5	-IORD Data Setup	50	35	20	20	20	15	10	-	ns
	(minimum)
t6	-IORD Data Hold	5	5	5	5	5	5	5	-	ns
	(minimum)
t6Z	-IORD Data Tristate	30	30	30	30	30	20	20	2	ns
	(maximum)
t7	Address Valid to IOCS16	90	50	40	N/A	N/A	N/A	N/A	4	ns
	Assertion (maximum)
t8	Address Valid to IOCS16	60	45	30	N/A	N/A	N/A	N/A	4	ns
	Released (maximum)
t9	-IORD/-IOWR to	20	15	10	10	10	10	10	-	ns
	Address Valid Hold
tRD	Read Data Valid to	0	0	0	0	0	0	0	-	ns
	IORDY Active
	(minimum), if IORDY is
	initially low after tA
tA	IORDY Setup Time	35	35	35	35	35	N/A5	N/A5	3	ns
tB	IORDY Pulse Width	1250	1250	1250	1250	1250	N/A5	N/A5	-	ns
	(maximum)
tC	IORDY Assertion to	5	5	5	5	5	N/A5	N/A5	-	ns
	Release (maximum)

Notes:

1.The symbol t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i must be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device’s identify device data.

2.This parameter specifies the time from the negation edge of -IORD to the time that the data bus is no longer driven by the Drive (tristate).

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4300D-00DSR PAGE 14 FEBRUARY 27, 2009