Toshiba AR-B1375, AR-B1376, 386SX manual O Channel Signal Description, Name Description

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AR-B1375/AR-B1376 User s Guide

(3) I/O Channel Signal Description

Name

Description

BUSCLK [Output]

The BUSCLK signal of the I/O channel is asynchronous to

 

the CPU clock.

RSTDRV [Output]

This signal goes high during power-up, low line-voltage or

 

hardware reset

SA0 - SA19

The System Address lines run from bit 0 to 19. They are

[Input / Output]

latched onto the falling edge of "BALE"

LA17 - LA23

The Unlatched Address line run from bit 17 to 23

[Input/Output]

 

SD0 - SD15

System Data bit 0 to 15

[Input/Output]

 

BALE [Output]

The Buffered Address Latch Enable is used to latch SA0 -

 

SA19 onto the falling edge. This signal is forced high

 

during DMA cycles

-IOCHCK [Input]

The I/O Channel Check is an active low signal which

 

indicates that a parity error exist on the I/O board

IOCHRDY

This signal lengthens the I/O, or memory read/write cycle,

[Input, Open collector]

and should be held low with a valid address

IRQ 3-7, 9-12, 14, 15

The Interrupt Request signal indicates I/O service request

[Input]

attention. They are prioritized in the following sequence :

 

(Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest)

-IOR

The I/O Read signal is an active low signal which instructs

[Input/Output]

the I/O device to drive its data onto the data bus

-IOW[Input/Output]

The I/O write signal is an active low signal which instructs

 

the I/O device to read data from the data bus

-SMEMR[Output]

The System Memory Read is low while any of the low 1

 

mega bytes of memory are being used

-MEMR

The Memory Read signal is low while any memory location

[Input/Output]

is being read

-SMEMW[Output]

The System Memory Write is low while any of the low 1

 

mega bytes of memory is being written

-MEMW

The Memory Write signal is low while any memory location

[Input/Output]

is being written

DRQ 0-3, 5-7 [Input]

DMA Request channels 0 to 3 are for 8-bit data transfers.

 

DMA Request channels 5 to 7 are for 16-bit data transfers.

 

DMA request should be held high until the corresponding

 

DMA has been completed. DMA request priority is in the

 

following sequence:(Highest) DRQ 0, 1, 2, 3, 5, 6, 7

 

(Lowest)

-DACK 0-3, 5-7

The DMA Acknowledges 0 to 3, 5 to 7 are the

[Output]

corresponding acknowledge signals for DRQ 0 to 3 and 5

 

to 7

AEN [output]

The DMA Address Enable is high when the DMA controller

 

is driving the address bus. It is low when the CPU is driving

 

the address bus

-REFRESH

This signal is used to indicate a memory refresh cycle and

[Input/Output]

can be driven by the microprocessor on the I/O channel

TC [Output]

Terminal Count provides a pulse when the terminal count

 

for any DMA channel is reached

SBHE [Input/Output]

The System Bus High Enable indicates the high byte SD8 -

 

SD15 on the data bus

3-4

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Contents 386SX CPU Card Page Table of Contents Using Memory Banks Placement & Dimensions Bios ConsoleSpecifications & SSD Types Supported Programming RS-485 & IndexPreface Static Electricity Precautions OrganizationIntroduction OverviewPacking List Features DMA Controller System ControllerMicroprocessor DMA ControllerKeyboard Controller Interrupt ControllerHex Range Device 1 I/O Port Address Map2 I/O Channel Pin Assignment Bus I/O Port Address MapI/O Channel Pin Assignments Address Description TimerREAL-TIME Clock and NON-VOLATILE RAM Real-Time Clock & Non-Volatile RAMReceiver Buffer Register RBR Interrupt Enable Register IERSerial Port Transmitter Holding Register THRLine Status Register LSR Line Control Register LCRModem Control Register MCR Modem Status Register MSRRegister Address Parallel PortDivisor Latch LS, MS Printer Interface LogicPrinter Status Buffer Error Slct PE -ACK -BUSYPrinter Control Latch & Printer Control Swapper Page Setting UP the System OverviewPin Mini DIN Keyboard Connector CN3 System SettingKeyboard Connector AUX. Keyboard Connector J4Pin PC/104 Connector Bus C & D CN1 2 PC/104 ConnectorPin PC/104 Connector Bus a & B CN2 O Channel Signal Description Name DescriptionPin Signal Hard Disk IDE Connector CN4I/O Channel Signal’s Description HDD Pin AssignmentParallel Port Connector CN6 FDD Port Connector CN5CN6 RS-485 Terminator JP7 Serial PortRS-232/RS-485 Select for COM-B JP2 External RS-485 Adapter Select J6 & J7External Power LED Header J2 Reset Header J1RS-232 Connector CN7 & DB2 LED HeaderBattery Charger Select JP3 Power Connector J3External Battery External Speaker Header J5CPU Base Clock Select JP1 Dram ConfigurationExternal Battery Connector J11 SIMM1 SIMM2CRT/LCD Flat Panel Display Connecting the CRT MonitorVGA Setting JP5 IRQ 9 Used SelectCRT Connector DB1 LCD Flat Panel DisplayLCD Control Connector CN9 LCD ConnectorDE/E Signal from M or LP Select JP6 JP6 Inverter Board DescriptionLCD Display Assignment LCD Panel Display Connector CN8Supported LCD Panel Manufacture Model No DescriptionInstallation Utility DisketteWIN 95 Driver VGA DriverWIN 3.1 Driver StepSSD Utility RFG.EXE Write Protect Function RFGDEMO.PGFHardware Write Protect Enable the Software Write ProtectDisable the Software Write Protect Software Write ProtectTime-Out Setting Watchdog TimerWatchdog Timer Setting LEDWatchdog Timer Trigger Watchdog Timer EnabledWatchdog Timer Disabled Switch Setting Solid State DiskSSD Firmware Address Select SW1-2 Overview2 I/O Port Address Select SW1-1 DEVICE=C\DOS\EMM386.EXE X=C800-C9FFSimulate 2 Disk Drive SSD Drive Number SW1-3 & SW1-4Flash Eprom Sram ROM Type Select SW1-5 & SW1-6 Disk Drive Name ArrangementJumper Setting M1~M3 & JP4 Memory Type SettingSwitch and Jumper Setting ROM Disk InstallationUV Eprom 27Cxxx Software Programming Large Page 5V Flash DiskJP4 \PGM137X ROM pattern file name Using Tool Program Small Page 5V Flash ROM DiskTyping DOS Command RAM DiskCombination of ROM and RAM Disk \FORMAT RAM disk letter /UPage Bios Console Bios Setup OverviewFloppy Setup Standard Cmos SetupDate & Time Setup Hard Disk SetupAdvanced Cmos Setup Hard Disk Delay Password CheckWait for ‘F1’ If Error System KeyboardAdvanced Chipset Setup Password Checking Password SettingSetting Password Load Default SettingSave Settings and Exit Auto Configuration with Fail Safe SettingBios Exit Bios UpdateFile of AMIFLASH.EXE had to Version Specifications Specifications & SSD Types SupportedSSD Types Supported Winbond AtmelSST FujitshuCS1 CS0 Using Memory BanksRegister Port SocketPage Placement & Dimensions PlacementDimensions Initialize COM port Programming RS-485 & IndexProgramming RS-485 Send out one character TransmitOUT &H3FC, INP&H3FC and &HEF Return OUT &H3FC, INP%H3FC and &HFA ReturnPrint #1, OUTCHR$ INPSTR$ ReturnName Function

386SX, AR-B1376, AR-B1375 specifications

The Toshiba AR-B1375 and AR-B1376 are notable embedded computing solutions that incorporate the 386SX microprocessor architecture. Designed for various applications, these models focus on reliability, performance, and versatility, making them appealing choices for system integrators and developers.

At the core of the AR-B1375 and AR-B1376 is the Intel 386SX microprocessor. This landmark processor marked a significant advancement in computing technology, introducing a 32-bit architecture while maintaining compatibility with 16-bit applications. The 386SX is known for its efficient processing capabilities, offering both multitasking support and enhanced memory management. It operates at clock speeds ranging typically from 16 MHz to 25 MHz, contributing to its effectiveness in running industrial applications.

One of the key features of the AR-B1375 and AR-B1376 systems is their modular architecture, which allows for easy customization and expansion. This modularity means users can tailor the hardware according to specific requirements, making it suitable for a wide range of applications such as automation, telecommunications, and embedded systems.

Both models support various I/O options, ensuring seamless integration with peripherals and external devices. They typically come equipped with serial and parallel ports, as well as support for modern interfaces like USB. The systems also feature onboard expansion slots, enabling the addition of further functionality, such as additional memory or specialized processing units.

In terms of memory, the AR-B1375 and AR-B1376 support a range of RAM configurations, allowing users to scale their systems based on the application demands. The inclusion of EPROM and EEPROM options also facilitates easy updates and programmability, which is crucial for embedded systems that often require firmware adjustments over time.

Moreover, these models are known for their robust thermal management features, which are essential in industrial environments where conditions can be harsh. This capability ensures stable performance and longevity, reducing the risk of system failures due to overheating or environmental factors.

To summarize, the Toshiba AR-B1375 and AR-B1376, coupled with the 386SX microprocessor, offer a blend of performance, flexibility, and reliability. Their modular design, extensive I/O support, and memory scalability make them ideal for a variety of embedded computing applications, placing them as commendable options in the world of industrial computing solutions. These systems not only exemplify Toshiba's commitment to innovation but also contribute significantly to the functionality of embedded technologies in a rapidly evolving industry.