SieMo S50037 Data Book PRELIMINARILY
PCM Timing
Symbol | Parameter | Min | Typ | Max | Unit |
fCLK | PCM clock frequency |
| 256 |
| kHz |
(1) | Clock duty cycle |
| 50 |
| % |
|
|
| |||
tsy:hd | Hold time from CLK low to SYNC high |
| 1.95 |
| us |
tsy:su |
| 1.95 |
| us | |
tsdat:dt | Delay time from CLK to valid MSB data |
|
| 50 | ns |
tdat:dt | Delay time from CLK high to PCM_OUT |
|
| 50 | ns |
| valid data |
|
|
|
|
tfdat:dt | Delay time from SYNC or CLK, whichever |
|
| 3009 | ns |
| is later, to PCM_OUT data line high |
|
|
|
|
| impedance |
|
|
|
|
tsy:low | Hold time from 2nd CLK to SYNC low |
|
| 3001 | ns |
tdr:su | 3001 |
|
| ns | |
tdr:hd | Hold time for CLK low to PCM_IN invalid | 3001 |
|
| ns |
figure 12 PCM Master Timing
9Assumes normal system clock operation. Figures may vary during low power modes when system clock speeds are reduced.
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