ADC ADDC1 instruction manual Connections, Balanced Analog Line Inputs, Clock Reference Input

Page 7

Connections

Balanced Analog

Auxiliary Digital Output,

Clock Reference Input,

Line Inputs (XLR)

BNC (AES)

BNC (AES, Wordclock, Superclock)

Left

Right

 

Aux 24 or 16-Bit

AES/EBU

AES,

 

 

 

Digital Output

 

WC,

 

 

 

 

 

SC

 

 

 

 

 

Ref In

 

 

SPDIF,

ADAT/SPDI F

 

 

 

 

AES

 

WC

 

 

 

 

 

 

 

 

 

Out

Analog Line In

 

Main 24-Bit Digital Outputs

 

 

Main Digital Output,

Main Digital Output,

Main Digital Output,

Wordclock Reference

BNC (SPDIF/AES)

TOSLINK Optical (ADAT /SPDIF)

XLR (AES /EBU)

Output, BNC

Balanced Analog Line Inputs

Left and Right balanced inputs use locking Neutrik™ gold-pin female XLR jacks. These inputs have a wide operating range. The input sensitivity (at 0 dBFS) ranges from -20 dBu (at maximum gain) to +29 dBu (at minimum gain). The input impedance is 200k Ohms balanced, and 100k Ohms unbalanced. The high input impedance and input sensitivity, allow direct connections from many instrument pickups (adapter cable required). Direct connection of piezo pickups is not recommended as these pickups require higher input impedances (to prevent low-frequency roll-off problems).

•XLR pin 2 = + Audio In

•XLR pin 3 = - Audio In

•XLR pin 1 = Cable Shield (grounded directly to the chassis to prevent internal ground loops)

2.Connect ground (sleeve on ¼” phone plug, case on RCA plug) to XLR pins 3 and 1.

Note it is best to used balanced wiring (“+”, “-“, “shield”) and to tie the “-“and “shield” at the unbalanced connector.

Clock Reference Input

This input auto-detects AES/EBU, SPDIF, Word Clock, or Super Clock signals, and automatically follows changes in sample-rate. When Auto mode is active the ADC1 will lock to the external clock source. Benchmark’s UltraLock circuitry isolates the conversion clock from any jitter present on the clock reference. Auto Mode will not degrade the conversion quality of the ADC1 even when very high levels of jitter are present on the clock reference.

To adapt to unbalanced sources

1.Connect “+” or hot (tip on ¼ phone plug, center pin on RCA plug) to XLR pin 2.

ADC1 Instruction Manual

Page 7

Page 6 Page 8
Image 7
Page 6 Page 8
Contents Channel 24-bit 192-kHz Audio Analog-to-Digital Converter Benchmark ADC1Federal Communications Commission FCC Notice Only Safety InformationContents Overview Page Features To adapt to unbalanced sources ConnectionsBalanced Analog Line Inputs Clock Reference InputAES/EBU XLR Output Digital OutputsOptical Output SPDIF/AES BNC Main and Aux Outputs Adat Optical Output ModeAdat S/MUX2 Optical Output Mode Adat S/MUX4 Optical Output ModeWord Clock Reference Output AC Power Entry ConnectorFuse Holder Programming the Outputs Mode Switch and DisplayTo program the conversion mode OperationTo select a fixed sample frequency on the Main Outputs Selecting a Fixed Frequency Using the Internal Clock SourceReading Sample Rates off of the Mode Display To synchronize with an external clock sourceMeter Display Resetting the ADC1 to Factory Default SettingsProgramming the Aux Output Adat or AES/EBU on the Optical OutputFirst Stage Gain Adjusting Input GainSecond Stage Gain Controls Rack Mounting MUX should not be used for Sample Rate Conversion Using Adat S/MUXProper S/MUX Identification is a Must Sample Rate is the Key that Controls S/MUXUltraLock … What is It? Put UltraLock converters to the test Problem #1What UltraLock converters cannot do Frequency Response PerformanceInter-Channel Phase Response THD+N vs. Level, 1 KHz KHz LPF unweighted32K B-H FFT, Idle Channel Noise 32K B-H FFT, -3 dBFS, 1 KHz 32K B-H FFT, -3 dBFS, 10 KHz Analog Audio Inputs SpecificationsWorldclock Reference Output Digital Audio Outputs Audio Performance LED Status Indicators Group Delay LatencyDimensions AC Power RequirementsWeight Page Benchmark 1 Year Warranty Warranty InformationBenchmark Extended Warranty Benchmark Extended 5* Year WarrantyBenchmark Media Systems, Inc
Top Page Image Contents