Panasonic MN103S manual Timer 1 Base Register TM1BR 0x0000A149

Page 14

Chapter 3

Microcomputer Basics 1

Register description

Group 4 Interrupt Control Register (G4ICR: 0x00008910)

bp

Flag name

Description

 

 

 

15

 

 

 

 

G4LV2

Group 4 interrupt priority level

14-12

G4LV1

Set a level from 6 to 0.

 

G4LV0

 

 

 

 

 

11-10

 

 

 

 

 

Timer 1 underflow interrupt enable flag

9

G4IE1

0: Disabled

 

 

1: Enabled

 

 

 

 

 

Timer 0 underflow interrupt enable flag

8

G4IE0

0: Disabled

 

 

1: Enabled

 

 

 

7-6

 

 

 

 

 

Timer 1 underflow interrupt request flag

5

G4IR1

0: No interrupt request

 

 

1: Interrupt request

 

 

 

 

 

Timer 0 underflow interrupt request flag

4

G4IR0

0: No interrupt request

 

 

1: Interrupt request

 

 

 

3-2

 

 

 

 

 

Timer 1 underflow interrupt detection flag

1

G4ID1

0: No interrupt detected

 

 

1: Interrupt detected

 

 

 

 

 

Timer 0 underflow interrupt detection flag

0

G4ID0

0: No interrupt detected

 

 

1: Interrupt detected

 

 

 

Timer 1 Base Register (TM1BR: 0x0000A149)

bp

7

6

5

4

3

2

1

0

Flag name

Description

TM1BR7

 

TM1BR6

 

TM1BR5

 

TM1BR4

Timer 1 Base Register

TM1BR3

 

TM1BR2

 

TM1BR1

 

TM1BR0

 

 

 

III−38 8-bit timer operation

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Contents MN103S927/92A/F92G LSI Application Notes Excerption Page Page About This Manual Format used for sample program explanations About This Manual3 Page Table of Contents Microcomputer Basics Chapter overview Appendix Table of Contents Hardware allocation list Counting rising edges using the event countOverview Timer 1 Base Register TM1BR 0x0000A149 Port 3 I/O Control Register P3DIR 0x0000A023 Timer 1 Binary Counter TM1BC 0x0000A151Timer 1 Mode Register TM1MD 0x0000A141 Port 3 Output Mode Register P3MD 0x0000A033 Flowchart ENDEnable the interrupt Example programCpum Inquiries URL http//panasonic.co.jp/semicon/e-micom/inquirySales Offices