Panasonic MN103S Timer 1 Binary Counter TM1BC 0x0000A151, Timer 1 Mode Register TM1MD 0x0000A141

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Chapter 3

Microcomputer Basics 1

Timer 1 Binary Counter (TM1BC: 0x0000A151)

bp

7

6

5

4

3

2

1

0

Flag name

Description

TM1BC7

 

TM1BC6

 

TM1BC5

 

TM1BC4

Timer 1 binary counter

TM1BC3

 

TM1BC2

 

TM1BC1

 

TM1BC0

 

 

 

Timer 1 Mode Register (TM1MD: 0x0000A141)

bp

Flag name

Description

 

 

 

 

 

Timer operation enable

7

TM1CNE

0: Operation disabled

 

 

1: Operation enabled

 

 

 

 

 

Timer initialization

 

 

0: Normal operation

6

TM1LDE

1: Initialization

 

 

TM1BR value is loaded into TM1BC.

 

 

Timer pulse output 1 is reset to low level.

 

 

 

5-3

 

 

 

 

 

Count source selection

 

 

000: IOCLK

 

TM1CK2

001: IOCLK/8

 

010: IOCLK/32

2-0

TM1CK1

011: Cascading with Timer 0

 

TM1CK0

100: Timer 0 underflow

 

 

101: Setting not available

 

 

110: Timer 2 underflow

 

 

111: TM1IO pin input

 

 

 

Port 3 I/O Control Register (P3DIR: 0x0000A023)

bp

7

6-0

Flag name

Description

P36D

 

P35D

 

P34D

P36 to P30 I/O control

P33D

0: Input mode

P32D

1: Output mode

P31D

 

P30D

 

 

 

8-bit timer operation

III−39

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Contents MN103S927/92A/F92G LSI Application Notes Excerption Page Page About This Manual Format used for sample program explanations About This Manual3 Page Table of Contents Microcomputer Basics Chapter overview Appendix Table of Contents Counting rising edges using the event count OverviewHardware allocation list Timer 1 Base Register TM1BR 0x0000A149 Timer 1 Binary Counter TM1BC 0x0000A151 Timer 1 Mode Register TM1MD 0x0000A141Port 3 I/O Control Register P3DIR 0x0000A023 Port 3 Output Mode Register P3MD 0x0000A033 END FlowchartExample program Enable the interruptCpum URL http//panasonic.co.jp/semicon/e-micom/inquiry InquiriesSales Offices