Maxtor 2B010H1, 2B015H1, 2B020H1 manual Reset and Interrupt Handling

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HOST SOFTWARE INTERFACE

Reset and Interrupt Handling

Reset Handling

One of three different conditions may cause a reset: power on, hardware reset or software reset. All three cause the interface processor to initialize itself and the Task File registers of the interface. A reset also causes a set of the Busy bit in the Status register. The Busy bit does not clear until the reset clears and the drive completes initialization. Completion of a reset operation does not generate a host interrupt.

Task File registers are initialized as follows:

Error		1
Sector	Count	1
Sector	Number	1
Cylinder Low		0
Cylinder High		0
Drive/Head		0

Interrupt Handling

The drive requests data transfers to and from the host by asserting its IRQ 14 signal. This signal interrupts the host if enabled by bit 1 (IRQ enable) of the Fixed Disk Control register.

Clear this interrupt by reading the Status register, writing the Command register, or by executing a host hardware or software reset.

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Contents Maxtor 541DX Product Manual Before You Begin U T I O NContents Product Specifications Handling and InstallationAT Interface Description Interface CommandsHost Software Interface Service and Support GlossaryFigures Introduction MaxtorCorporationManualOrganization AbbreviationsConventions Key Features ProductDescriptionFunctional / Interface Product FeaturesModels CYL SP T MAX LBA Capacity CacheManagement Major HDA Components SubsystemConfiguration Jumper Location / ConfigurationJumper Configuration Cylinder Limitation Jumper DescriptionProductSpecifications Drive ConfigurationPerformanceSpecifications Models and CapacitiesPhysical Dimensions Param Eter Valu EPowerRequirements Power Mode DefinitionsEPA Energy Star Compliance Environmental LimitsShock and Vibration Reliability SpecificationsParam Eter Oper AT ING ON- Oper AT ING Safety Regulatory Compliance EMC/EMIHard Drive Handling Precautions HandlingandInstallationElectro-Static Discharge ESD Unpacking and Inspection Multi-pack Shipping ContainerPhysical Installation RepackingBefore You Begin Hook upSet up Start upInterfaceConnector ATInterfaceDescriptionPinDescriptionSummary PIN IGN ALPIN Name Signal Name Signal Desc Ription Pin Description TableIM in G Paramet ERS Mode PIO TimingImin G Paramet ERS Mode DMATimingUltra DMA Timing ModeSustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst Task File Registers HostSoftwareInterfacePOR T EAD WR ITE Conten TS LBA Bits CommandRegister Seek, Format, and Diagnostic CommandsSummary M M a N D N a M E M M a N D code PA R a M E T E R S U S E DControl Diagnostic Registers Reset and Interrupt Handling InterfaceCommands ReadCommands Read DMA WriteCommands Write Multiple VAL UE DES C RIP Tion ModeSet/CheckCommandsEC TOR LE VE L VAL UE Omman D PowerModeCommands Timer VAL UE TIME-OUT PeriodSleep Mode InitializationCommands Or D ENT Desc RiptionOr D 15- 10, as c urrently defined Initialize Drive Parameters Seek,FormatandDiagnosticCommands ER ROR Code Desc RiptionA.R.T. CommandSet Key RegisterServiceandSupport Service PolicyNo Quibble Service Product SupportFrom Dial Glossary Correctable error Central processing unit CPUChannel CharacterDirect access Direct memory access DMAError correction code ECC Error freeHard error Head disk assembly HDAFrequency response Gigabyte GBLate window LatencyLogic Logical addressPhase locked loop PLL Phase marginRandom access memory RAM Read gate signalSector pulse signal Seek complete signalSequential access Soft errorStrobe offset signal Un-correctable errorUnrecoverable error Write gate signal