Maxtor 2B015H1, 2B010H1, 2B020H1 manual Write Multiple

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INTERFACE COMMANDS

Write Multiple

Performs similarly to the Write Sector(s) command, except that:

1.The controller sets BSY immediately upon receipt of the command,

2.Data transfers are multiple sector blocks and

3.The Long bit and Retry bit is not valid.

Command execution differs from Write Sector(s) because:

1.Several sectors transfer to the host as a block without intervening interrupts.

2.DRQ qualification of the transfer is required at the start of the block, not on each sector.

The block count consists of the number of sectors to be transferred as a block and is programmed by the Set Multiple Mode command, which must be executed prior to the Write Multiple command. When the Write Multiple command is issued, the Sector Count register contains the number of sectors requested — not the number of blocks or the block count.

If the number of sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. This final, partial block transfer is for N sectors, where N = (sector count) modulo (block count)

The Write Multiple operation will be rejected with an Aborted Command error if attempted:

1.Before the Set Multiple Mode command has been executed, or

2.When Write Multiple commands are disabled.

All disk errors encountered during Write Multiple commands report after the attempted disk write of the block or partial block in which the error occurred.

The write operation ends with the sector in error, even if it was in the middle of a block. When an error occurs, subsequent blocks are not transferred. When DRQ is set at the beginning of each full and partial block, interrupts are generated.

Write DMA

Multi-word DMA

Identical to the Write Sector(s) command, except that:

1.The host initializes a slave-DMA channel prior to issuing the command,

2.Data transfers are qualified by DMARQ and are performed by the slave-DMA channel and

3.The drive issues only one interrupt per command to indicate that data transfer has terminated at status is available.

Ultra DMA

With the Ultra DMA Write protocol, the control signal (HSTROBE) that latches data from DD(15:0) is generated by the devices which drives the data onto the bus. Ownership of DD(15:0) and this data strobe signal are given to the host for an Ultra DMA data out burst.

During an Ultra DMA Write burst, the host always moves data onto the bus, and, after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a HSTROBE edge to latch the data. Both edges of HSTROBE are used for data transfers.

Any error encountered during Write DMA execution results in the termination of data transfer. The drive issues an interrupt to indicate that data transfer has terminated and status is available in the error register. The error posting is the same as that of the Write Sector(s) command.

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Contents Maxtor 541DX Product Manual U T I O N Before You BeginContents Handling and Installation Product SpecificationsInterface Commands AT Interface DescriptionHost Software Interface Glossary Service and SupportFigures MaxtorCorporation IntroductionManualOrganization AbbreviationsConventions ProductDescription Key FeaturesProduct Features Functional / InterfaceModels CYL SP T MAX LBA Capacity CacheManagement Major HDA Components Jumper Location / Configuration SubsystemConfigurationJumper Configuration Cylinder Limitation Jumper DescriptionDrive Configuration ProductSpecificationsPerformanceSpecifications Models and CapacitiesParam Eter Valu E Physical DimensionsPower Mode Definitions PowerRequirementsEPA Energy Star Compliance Environmental LimitsReliability Specifications Shock and VibrationParam Eter Oper AT ING ON- Oper AT ING EMC/EMI Safety Regulatory ComplianceHandlingandInstallation Hard Drive Handling PrecautionsElectro-Static Discharge ESD Multi-pack Shipping Container Unpacking and InspectionRepacking Physical InstallationHook up Before You BeginStart up Set upATInterfaceDescription InterfaceConnectorPinDescriptionSummary PIN IGN ALPin Description Table PIN Name Signal Name Signal Desc RiptionPIO Timing IM in G Paramet ERS ModeDMATiming Imin G Paramet ERS ModeMode Ultra DMA TimingSustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst HostSoftwareInterface Task File RegistersPOR T EAD WR ITE Conten TS LBA Bits Seek, Format, and Diagnostic Commands CommandRegisterM M a N D N a M E M M a N D code PA R a M E T E R S U S E D SummaryControl Diagnostic Registers Reset and Interrupt Handling InterfaceCommands ReadCommands Read DMA WriteCommands Write Multiple ModeSet/CheckCommands VAL UE DES C RIP TionEC TOR LE VE L VAL UE Omman D Timer VAL UE TIME-OUT Period PowerModeCommandsSleep Mode Or D ENT Desc Ription InitializationCommandsOr D 15- 10, as c urrently defined Initialize Drive Parameters ER ROR Code Desc Ription Seek,FormatandDiagnosticCommandsKey Register A.R.T. CommandSetService Policy ServiceandSupportNo Quibble Service Product SupportFrom Dial Glossary Central processing unit CPU Correctable errorChannel CharacterDirect memory access DMA Direct accessError correction code ECC Error freeHead disk assembly HDA Hard errorFrequency response Gigabyte GBLatency Late windowLogic Logical addressPhase margin Phase locked loop PLLRandom access memory RAM Read gate signalSeek complete signal Sector pulse signalSequential access Soft errorUn-correctable error Strobe offset signalUnrecoverable error Write gate signal
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