Hitachi 9960, 9900 Series manual

Hi-Star Architecture – An Internal Switched Hierarchical Star Network

control memory in its “split” configuration. Again, control memory is mirrored. This path topology is used to facilitate this mirrored architecture.

Either way the bandwidth is calculated in the CM-HSM, the bandwidth is 3.2GB/sec total when all of the processor modules are installed. 4 bits clocked at 100MHz equals 50MB/sec per path multiplied by 64 ports is 3.2GB/sec bandwidth. Or, the full 8-bit path clocked at 100MHz multiplied by the combined 32 ports of the control memory “pair” equals 3.2GB/sec total.

Figure 16 – Separate redundant control memory handles the exchange of control information between processors and cache memory about the status, location, and configuration of data.

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