Intel PCI-X, Intel Gigabit Ethernet Controllers 11.4.2 D3 State, No Link Required copper only

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PHY Functionality and Features

11.4.2D3 State, No Link Required (copper only)

Each time the MAC transitions to a D3 or D0u power-state with no link required (wakeup disabled and no manageability enabled), the PHY enters its IEEE power-down mode, consuming the least amount of power possible. When powered-down, the PHY does not perform any form of Energy Detection, and does not generate any energy (NLPs) on the wire itself.

MAC transitions back to D0 power-states, either through explicit system/software mechanisms or by hardware reset operations, return the PHY back to a functional power-state. This will also re- initiate an auto-negotiation attempt advertising all speeds possible (10/100/1000 Mbps)1, reverting to an Energy Detect state if unsuccessful in establishing link-up.

11.4.3D3 Link-Up, Speed-Management Enabled (copper only)

If the MAC is configured for PHY power management (CTRL.EN_PHY_PWR_MGMT = 1b) and the PHY is linked at 1000 Mbps, then upon MAC transitions to D3 or D0u power-states where link IS required (either wakeup or manageability are enabled), the PHY re-initiates an Auto- Negotiation operation, advertising only 10/100 Mbps capability. This results in D3 operation at a lower-speed link and a reduced power level.

If a wakeup, management operation, or other system event causes the MAC to revert to fully- operational D0 state, the PHY initiates another Auto-Negotiation operation, advertising all 10/100/ 1000 Mbps speed capability, in order to return to maximum-speed operation.

11.4.4D3 Link-Up, Speed-Management Disabled (copper only)

If the MAC is configured for no PHY power management (CTRL.EN_PHY_PWR_MGMT = 0b), and the MAC transitions to D3 power-states where link is required for either wakeup or manageability, then the PHY simply remains operational at its current line speed, without initiating a new Auto-Negotiation operation. This configuration is not recommended, since D3 power consumption at 1000 Mbps exceeds 20 mA Vaux.

1.Half duplex not supported.

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Contents 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, Software Developer’s Manual Date Version Comments Initial Public ReleaseSoftware Developer’s Manual Contents TCP Segmentation Use of Multiple Data Descriptors Software Developer’s Manual Vii Power Management 129 Introduction to Power Management 10.1.3 203 13.4.25 13.7.10 Appendix 82540EP/EM and 82545GM/EM Differences Xiv Scope OverviewCSA Features 82547GI/EI Only Ethernet Controller FeaturesPCI Features Network Side FeaturesHost Offloading Features Additional Performance Features Additional Ethernet Controller Features Technology FeaturesMemory Alignment Terminology ConventionsRelated Documents Register and Bit ReferencesArchitectural Overview IntroductionPHY External ArchitectureLAN a LAN B ECHO, Next Fext Eeprom FlashAGC, A/D Microarchitecture 1 PCI/PCI-X Core Interface2 82547GI/EI CSA Interface DMA Engine and Data Fifo4 10/100/1000 Mb/s Receive and Transmit MAC Blocks 5 MII/GMII/TBI/Internal SerDes Interface Block6 10/100/1000 Ethernet Transceiver PHY Eeprom InterfaceExample 2-1. Byte Ordering DMA AddressingFlash Memory Interface Little Endian Data OrderingIntel Architecture Byte Ordering Ethernet AddressingIA Byte # LSB MSB Interrupts Checksum Offloading Hardware Acceleration CapabilityBuffer and Descriptor Structure TCP SegmentationArchitectural Overview Packet Reception IntroductionPacket Address Filtering Receive Descriptor Format Receive Data StorageReceive Descriptor Rdesc Layout PIF Ipcs Tcpcs RSV Ixsm EOP Receive Descriptor Status FieldReceive Status RDESC.STATUS Layout ReceiveReceive Descriptor Errors Field RSV SEQ Receive Errors RDESC.ERRORS LayoutRXE IPE Tcpe RSV CXEPRI CFI Vlan Receive Descriptor Special FieldSpecial Descriptor Field Layout PRIReceive Descriptor Fetching Receive Descriptor Fetching AlgorithmReceive Descriptor Packing Receive Descriptor Write-BackReceive Descriptor Queue Structure Null Descriptor PaddingReceive Descriptor Ring Structure Receive Interrupt Delay Timer / Packet Timer Rdtr Receive Timer InterruptReceive Interrupts Receive Interrupt Absolute Delay Timer Radv Packet Delay Timer Operation State DiagramSmall Receive Packet Detect Receive Descriptor Minimum Threshold ICR.RXDMT 8 82544GC/EI Receive InterruptsReceive Packet Checksum Offloading Receiver Fifo OverrunSupported Receive Checksum Capabilities Packet Type HW IP Checksum HW TCP/UDP Checksum CalculationPacket Type HW IP Checksum HW TCP/UDP Checksum MAC Address FilterGC/EI Supported Receive Checksum Capabilities Packet Type HW IP Checksum9.3 IPv4 Filter Packet TransmissionSNAP/VLAN Filter 9.4 IPv6 FilterTransmit Data Storage Transmit DescriptorsTransmit Descriptor Tdesc Layout Transmit Descriptor Tdesc Layout Legacy ModeLegacy Transmit Descriptor Format Transmit Descriptor Legacy DescriptionsSTA Transmit Descriptor Description LegacyCMD CSSIDE VLE Dext RSV Transmit Descriptor Command Field Format10. Transmit Command TDESC.CMD Layout Ifcs EOPTransmit Descriptor Status Field Format 11. Transmit Status LayoutTransmit Descriptor Special Field Format 12. Special Field TDESC.SPECIAL Layout5 TCP/IP Context Transmit Descriptor Format 6 TCP/IP Context Descriptor Layout 13. Transmit Descriptor Tdesc Layout Type = 0000b14. Transmit Descriptor Tdesc Layout Transmit Description Descriptor OffloadTucmd 6.1 TCP/UDP Offload Transmit Descriptor Command FieldTransmit Description DtypIDE RSV Dext TSE TCP 15. Command Field TDESC.TUCMD Layout82544GC/EI only 6.2 TCP/UDP Offload Transmit Descriptor Status Field 7 TCP/IP Data Descriptor Format16. Transmit Status Layout Popts RSV STA Dcmd Dtyp Dtalen 17. Transmit Descriptor Tdesc Layout Type = 0001bPopts IDE VLE Dext 7.1 TCP/IP Data Descriptor Command Field18. Command Field TDESC.DCMD Layout TSE Ifcs EOP19. Transmit Status Layout 7.2 TCP/IP Data Descriptor Status FieldReserved 20. Packet Options Field TDESC.POPTS Layout 7.3 TCP/IP Data Descriptor Option Field7.4 TCP/IP Data Descriptor Special Field RSV Txsm IxsmTransmit Descriptor Ring Structure 21. Special Field TDESC.SPECIAL LayoutTransmit Descriptor Ring Structure Transmit Descriptor Fetching Transmit Descriptor Write-backTransmit Interrupts Delayed Transmit Interrupts Assumptions Transmission ProcessTCP Segmentation Data Fetch Control TCP Segmentation PerformancePacket Format TCP/UDP Data FCSTCP Segmentation Indication 3936TCP Segmentation Use of Multiple Data Descriptors TCP Partial Pseudo-Header ChecksumVersion IP Hdr IP and TCP/UDP HeadersOptions Fragment Offset Low Type of service Version IP Hdr Length FragmentOffset High Header Checksum Length Checksum Urgent Pointer Options Destination Port Sequence NumberTCP Header Byte1 Byte0 Destination PortSource Port Destination Port Length Checksum Byte3 Byte2 Byte1 Byte017. UDP Pseudo Header Diagram for IPv4 Transmit Checksum Offloading with TCP Segmentation9 IP/TCP/UDP Header Updating 19. Overall Data Flow 9.1 TCP/IP/UDP Header for the First Frame 9.2 TCP/IP/UDP Header for the Subsequent FramesIP/TCP/UDP Transmit Checksum Offloading 9.3 TCP/IP/UDP Header for the Last FrameIpcss Receive and Transmit Description Address Description PCI ConfigurationMandatory PCI Registers PCISpecification Update for the latest stepping information Base Address Registers AddrAll base address registers have the following fields Field Bits Read Initial Description Write ValueExpansion ROM Base Address Offset SpaceCapabilities Linked List Address Next PointerPCI definition for more details Bits Initial Value DescriptionStatus Register Layout 82547GI/EINext Capability PCI-X Configuration RegistersPCI-X Capability ID Byte OffsetWrite Value PCI-X CommandBits Read Initial Maximum Memory Read Byte Count. This register setsUSC SCD PCI-X StatusBits Read Intial Description Write Value Command Register as follows Reserved and Undefined AddressesMSI Capability ID Message Signaled Interrupts1Message Signaled Interrupt Configuration Registers Bits Read Initial Description Write Value 05hMessage Control 3.1.5 Message Upper Address Commands3.1.4 Message Address 3.1.6Transaction Target PCI Commands PCI-X Commands Accepted PCI/PCI-X Command as a TargetPCI Commands Abr PCI-X Commands Transaction Cause PCI Commands PCI-X CommandsPCI/PCI-X Command Usage Memory Write OperationsMaster Write Command Usage Algorithm MWI BurstsMW Bursts PCI-X Command UsageMemory Read Operations Rules for Memory Read OperationsCache Line Information1 Outstanding Memory ReadInterrupt Assignment 82547GI/EI Only LAN DisableTarget Transaction Termination CardBus Application 82541PI/GI/EI Only Eeprom Interface General OverviewComponent Identification Component Identification Via Programming InterfaceStepping Vendor ID Device ID Description Eeprom Device and Interface Software Access Signature and CRC FieldsEeupdate Utility Command Line ParametersWord Used Bit Image Eeprom Address Map1Ethernet Controller Address Map For the 82541xx and 82547GI82541xx and 82547GI/EI only LAN a82545GM 82540EP 82546GB/EB only82541xx 82545GM82540EP/EM ASFGC/EI and 82541ER Eeprom Address Map Word Description Default HW AccessAddress Hi Byte Low Byte Software Compatibility Word Word 03h Ethernet Address Words 00h-02hSoftware Compatibility Word Word 03h Bit Name DescriptionCompatibility Fields Word 05h 07h SerDes Configuration Word 04hEeprom Image Version Word 05h PBA Number Word 08h, 09hInitialization Control Word 1 Word 0Ah Initialization Control Word 1 Word 0AhSubsystem ID Word 0Bh Subsystem Vendor ID Word 0ChInitialization Control Word 2 Word 0Fh Device ID Word 0Dh, 11h1Vendor ID Word 0Eh Initialization Control Word 2 Word 0Fh82541PI/GI Only PHY Register Address Data Words 10h, 11h, and 13h 1Eh Common Power Word 12hSoftware Defined Pins Control Word 10h1, 20h OEM Reserved Words Words 10h, 11h, 13h 1FhSoftware Defined Pins Control Word 10h, 20h CSA Port Configuration 2 Word 21h CSA Port Configuration 2 Word 21hBit Description Default Circuit Control Word 21h 20 D0 Power Word 22h high byte21 D3 Power Word 22h low byte Reserved Words 23h 2EhManagement Control Word 13h1, 23h2 10. Initial Management Control Register Settings82541PI/GI/EI and 82547GI/EI Only SMBus Slave Address Word 14h1 low byte, 24h low byte 11. SMBus Slave Address82546GB/EB uses INTB# Initialization Control 3 Word 14h1 high byte, 24h high byte12. Initialization Control For Address 24h High Byte / LAN a27 IPv4 Address Words 15h 16h1 and 25h 26h LED Configuration Defaults Word 2Fh2Boot Agent Main Setup Options Word 30h 28 IPv6 Address words 17h 1Eh1 and 27h 2Eh15. Boot Agent Main Setup Options DBS Boot Agent Configuration Customization Options Word 31hBBS Mode 16. Boot Agent Configuration Customization Options Word 31hSIG DFUBoot Agent Configuration Customization Options Word 32h 17. Boot Agent Configuration Customization Options Word 32hIBA Capabilities Word 33h IBA Secondary Port Configuration Words 34h-35h18. IBA Capabilities Checksum Word Calculation Word 3Fh 19. WOL Mode and Functionality Word 0Ah20. WOL Mode and Functionality Word 20h Eeprom ImagesManufacturer Parallel Flash Memory21. Flash Memory Manufacturers Number124 Flash Control and Accesses Flash Interface OperationRead Accesses Write AccessesFlash Buffer Write Cycle 128 Introduction to Power Management AssumptionsPower States D3cold supportDr State 1.2 D0u State1.3 D0a D0 active Timing1.4 D3 Power Up Off to Dr to D0u to D0a Diagram #Transition From D0a to D3 and Back Without PCI Reset Transition from D0a to D3 and Back Without PCI ResetTransition From D0a to D3 and Back with PCI Reset RST#PCI Reset Without Transition to D3 PCI Reset SequenceCapability ID Byte Offset = 0 RO PCI Power Management RegistersBits Default Description Next Item Pointer Byte Offset = 1 ROReserved Power Management Capabilities PMC 2 Bytes Offset = 2 ROEeprom Software Developer’s Manual 139 Byte Offset = 6 RO Pmcsrbse Bridge Support Extensions3.6 Data Register Byte Offset = 7 ROAdvanced Power Management Wakeup WakeupAcpi Power Management Wakeup Pre-Defined Filters Wakeup PacketsDirected Exact Packet 3.1.4 Magic Packet*1 3.1.3 BroadcastDirected Multicast Packet Offset Field Value Action CommentOffset Field Value Action Comment Bytes + D + S a 3.1.5 ARP/IPv4 Request Packet1+ S a ARPDirected IPv4 Packet1 Offset # of bytes Field Value Action CommentDirected IPv6 Packet1 + S IPX Diagnostic Responder Request Packet Example1Flexible Filter + D + SDirected IPX Packet Example 3.4 IPv6 Neighbor Discovery Filter1Wakeup Packet Storage CRC152 Ethernet Interface Link Interfaces OverviewInternal SerDes Interface/TBI Mode- 1Gb/s1 1.2 8B10B Encoding/DecodingCode Group and Ordered Set Usage Gmii 1 Gb/sCode Groups and Ordered Sets Code OrderedSetDuplex Operation Internal Interface1MII 10/100 Mb/s Full Duplex Half DuplexCarrier Extension 1000 Mb/s Only Packet BurstingAuto-Negotiation and Link Setup1 Auto-Negotiation and Link Setup2Link Speed Link Configuration in Internal Serdes/TBI Mode1Auto-Negotiation TXCW.txConfigWord Hardware Auto-NegotiationSoftware Auto-Negotiation Bit DescriptionInternal GMII/MII Mode Forcing LinkUsing Auto-Speed Detection ASD Forcing SpeedMII Management Registers Automatic Detection of Link Speed using SPD-INDDuplex Comments Regarding Forcing LinkInternal Serdes1 Mode Software Enabled Internal SerDes Mode1 Control Bit ResolutionInternal Serdes Mode1 Hardware Enabled Control Bit Effect on Control BitsGMII/MII Mode PHY Speed Indication Internal PHY Mode Control Bit ResolutionInternal Serdes Mode1 Auto-Negotiation Skipped GMII/MII Mode Auto-Speed Detection GMII/MII Mode Force SpeedInternal PHY Mode Loss of Signal/Link Status IndicationInternal Serdes Mode GMII/MII Mode Force Link10/100 Mb/s Specific Performance Enhancements Adaptive IFS110. Flow Control Registers Flow ControlMAC Control Frames & Reception of Flow Control Packets Register Name Description3x MAC Control Frame Format Discard Pause Frames and Pass MAC Control Frames Transmission of Pause FramesSoftware Initiated Pause Frame Transmission External Control of Flow Control Operation1Vlan Packet Format Comparison 802.1q Vlan Packet Format1 802.1q Tagged Frames Packet #OctetsAdding 802.1q Tags on Transmits Transmitting and Receiving 802.1q Packets802.1q Vlan Packet Filtering Stripping 802.1q Tags on ReceivesPacket Reception Decision Table VFE178 Configurable LED Outputs1 Selecting an LED Output SourcePolarity Inversion Blink ControlBlink Control 182 PHY Functionality and Features Auto-NegotiationRegister Update Next Page ExchangesPin 11.2 MDI/MDI-X Crossover copper onlyStatus 1000BASE-TPolarity Correction copper only 11.2.2 10/100 Downshift 82540EP/EM OnlyCable Length Detection copper only PHY Power Management copper onlyLink Down Energy Detect copper only 11.4.4 D3 Link-Up, Speed-Management Disabled copper only 11.4.3 D3 Link-Up, Speed-Management Enabled copper only11.4.2 D3 State, No Link Required copper only Mdio Control Mode InitializationDetermining Link State Overview of Link EstablishmentForced Operation Configuration ResultFalse Link Determining Duplex State Via Parallel DetectionParallel Detection Link CriteriaAuto Negotiation 11.7.1 1000BASE-T11.7.3 10BASE-T Using SmartSpeedLink Enhancements SmartSpeedAsmdir Settings Pause Setting Low Power OperationPause And Asymmetric Pause Settings Management Data InterfaceSmart Power-Down Powerdown via the PHY Register11.11 1000 Mbps Operation DSP ECHO, Next 4DPAM5 Transmit Functions Transmit FifoLine Driver Spectral ShaperLow-Pass Filter Transmit/Receive FlowReceive Functions Descrambler 11.12 100 Mbps Operation11.13 10 Mbps Operation Viterbi Decoder/Decision Feedback Equalizer DFEPHY Line Length Indication 202 Introduction1 Features of Each MAC12.2.1 PCI/PCI-X interface 204 12.2.3 SDP, LED, INT# output MAC Configuration Register SpaceIO BAR Eeprom Map Shared EepromEeprom Arbitration Flash Access Contention Shared FlashValues Sampled on Reset Pin sampled LAN device controlled Enable/DisableMulti-Function Advertisement Power ReportingInterrupt Use Interrupt Line Used EnabledSummary INTA#Register Descriptions Register ConventionsMemory-Mapped Access to Expansion ROM Memory-Mapped Access to Internal Registers and MemoriesMemory-Mapped Access to Flash Memory and I/O Address DecodingOffset Abbreviation Name Size IoaddrIodata IoaddrIodata Register Configurations AD C/BE#30 Bits82544GC/EI Ethernet Controller Register SummaryCategory Offset Abbreviation Name 82547GI/EI onlyIpat 82544GC PRC64 XofftxcFcruc Gprc82544GC/EI , 82541xx , or 82547GI/EI CategoryAbbreviation Name Register To the 82544GC/EI , 82541xx , or 82547GIPCI-X Register Access Split1 Device Control Register Main Register DescriptionsCtrl 00000h R/W Ctrl Register Bit Description Field Bits Initial Description ValueIlos SLUSpeed SDP1DATA FrcdplxSDP0DATA ADVD3WUCField Bits Initial Description Status 00008h R BEM = 0 64-bit mode Little-EndianDevice Status Register Little-Endian Data OrderingTxoff Status Register Bit DescriptionTbimode Pcixmode AsdvPCI66 PcixspdEecd Register Bit Description EEPROM/Flash Control & Data RegisterEecd 00010h R/W 82544GC/EI OnlyEepres EereqEegnt EesizeEerd 00014h RW Eeprom Read Register1Eeprom Read Register Bit Description Eeprom Read Register Bit Description 82541xx and 82547GI/EI Done StartFlash Access FLA Flash Access1FLA 0001Ch R/W 10. Ctrlext Register Bit Description Extended Device Control RegisterCtrlext 00018h, R/W 23 16SDP7IODIR SDP6IODIRSDP2IODIR AsdchkDown Vreg Power11. GPI to SDP Bit Mappings LinkmodeSwdpiohi Swdpinshi12 GC/EI Ctrlext Register Bit Description CTRL.RST13 GC/EI GPI to SDP Bit Mapping MDI Control Register Mdic 00020h R/WRegadd 14. MDI Control Register Bit DescriptionRSV PHY REG Data PhyaddRegister Mode Description 15. PHY Register Bit Mode DefinitionsPHY Registers Field Bits Description Mode HW Rst SW Rst MSB242 Enaxc LSBRO,L Software Developer’s Manual 245 246 For the 82541xx and 82547GI/EI 82544GC/EI only 82541xx Pause82541xx 82547GI/EI 82541xx and 82547GI/EI only ANEG2 82544GC/EI OnlyANEG3 RF1Software Developer’s Manual 251 23. Link Partner Ability Register Base Page Bit Description1 10BASE-T 82541xx and 82547GI/EI Only24. PHY Link Page Ability Bit Description1 100BASE-TX1b 82541xx Software Developer’s Manual 255 Bits Field Description Mode HW Rst SW Rst MASTER/SLAVE MasterANEG0 ANEG1258 Software Developer’s Manual 259 DIS NLP Preen SFDSoftware Developer’s Manual 263 264 Software Developer’s Manual 265 266 82541EI/82547GI B0 stepping 82541/GI/ER and 82547GI B1268 HCD NOK Software Developer’s Manual 271 272 Field Bits Description Mode HW Rst Ledactled SPEED100LED SPEED1000LED276 Software Developer’s Manual 277 51. MDI Register 30 Operations Documented MDI Register 30 Operations1To Perform Operation MDI Read/Write Sequence Fcal 00028h R/W Flow Control Address LowFlow Control Address High Fcah 0002Ch R/WFCT 00030h R/W Flow Control TypeVlan Ether Type VET 00038h R/W56. VET Register Bit Description Flow Control Transmit Timer ValueFcttv 00170h R/W 57. Fcttv Register Bit DescriptionTxcw 00178h R/W Transmit Configuration Word Register158. Txcw Register Bit Description Receive Configuration Word Register1 Rxcw 00180h R59. Rxcw Register Bit Description ANC LED Control1Ledctl 00E00h RW LED1 ACTIVITY# LED0 LINKUP#Mode Encodings for LED Outputs1 60. LED Control Bit Description161. Mode Encodings for LED Outputs Mode Pneumonic State / Event Indicated62. PBA Register Bit Description Packet Buffer AllocationPBA 01000H R/W Field Bits Initial Value DescriptionICR 000C0H R Interrupt Cause Read Register63. ICR Register Bit Description Rxcfg RXT0Mdac GPISDP6ITR 000C4h R/W Interrupt Throttling Register1Interval ICS 000C8h W Interrupt Cause Set Register64. ICS Register Bit Description 65. IMS Register Bit Description Interrupt Mask Set/Read RegisterIMS 000D0h R/W To the 82544GC/EIInterrupt Mask Clear Register IMC 000D8h W66. IMC Register Bit Description 67. Rctl Register Bit Description Receive Control RegisterRctl 00100h R/W SBPLBM MPELPE RdmtsVFE BAMBsize CfienBsex PmcfSecrc Fcrtl 02160h R/W XON Enable 82544GC/EI , 82541xx , and 82547GI/EI onlyFlow Control Receive Threshold Low 68. Fcrtl Register Bit DescriptionFcrth 02168h R/W Flow Control Receive Threshold High69. Fcrth Register Bit Description Rdbal 02800hR/W Receive Descriptor Base Address LowReceive Descriptor Base Address High Rdbah 02804h R/WRdlen 02808h R/W Receive Descriptor LengthReceive Descriptor Head RDH 02810h R/WRDT 02818hR/W Receive Delay Timer RegisterReceive Descriptor Tail Rdtr 02820h R/WReceive Interrupt Absolute Delay Timer1 Radv 0282Ch RWRsrpd 02C00h R/W Receive Small Packet Detect Interrupt1Transmit Control Register Tctl 00400hR/WPSP 76. Tctl Register Bit DescriptionCold TCTL.COLDRtlc Transmit IPG RegisterTipg 00410R/W Nrtu77. Tipg Register Bit Description IPGR2 IPGR1 IpgtAifs 00458R/W Adaptive IFS Throttle AITIPGR2 78. Aifs Register Bit Description Transmit Descriptor Base Address LowTdbal 03800h R/W 79. Tdbal Register Bit DescriptionTdbah 03804h R/W Transmit Descriptor Base Address HighTransmit Descriptor Length Tdlen 03808h R/WTDH 03810h R/W Transmit Descriptor Head82. TDH Register Bit Description TDT 03818h R/W Transmit Interrupt Delay ValueTransmit Descriptor Tail Tidv 03820h R/WTxdmac 03000h R/W TX DMA Control 82544GC/EI onlyTransmit Descriptor Control Txdctl 03828h R/W86. Txdctl Register Bit Description Lwthresh RSV1 Gran RSV Wthresh Hthresh PthreshGran Transmit Absolute Interrupt Delay Value1Tadv 0382Ch RW LwthreshTspbp Tsmt TCP Segmentation Pad And Minimum Threshold Tspmt 03830h RWTspbp Software Developer’s Manual 319 87. Rxdctl Register Bit Description Receive Descriptor ControlRxdctl 02828h R/W Wthresh RSV Hthresh Pthresh88. Rxcsum Register Bit Description Receive Checksum ControlRxcsum 05000h R/W 3111Tuofld IpofldIPV6OFL MTA1270 05200h-053FCh R/W Filter RegistersMulticast Table Array 89. MTA Register Bit DescriptionDestination Address RAL 05400h + 8*n R/W Receive Address LowReceive Address High RAH 05404h + 8∗n R/W91. RAH Register Bit Description Vlan Filter Table Array1VFTA1270 05600h 057FCh R/W RAHWUC 05800h R/W Wakeup RegistersWakeup Control Register 92. VFTA1270 Bit DescriptionApmpme Wakeup Filter Control RegisterWufc 05808h R/W SPMWakeup Status Register WUS 05810h R330 IP Address Valid Ipav 5838h R/WAddress 13.6.5 IPv4 AddressIP4AT 05840h 05858h R/W2 Field Dword # Address Bits Initial Value DescriptionIPV6ADDR0 13.6.6 IPv6 AddressIP6AT 05880h 0588Ch R/W Dword # Address Bits Initial Value DescriptionWakeup Packet Memory 128 Bytes Wakeup Packet LengthFlexible Filter Length Table LEN1 Flexible Filter Mask Table Ffmt 09000h 093F8h R/WLEN0 LEN2Flexible Filter Value Table Statistics RegistersFfvt 09800h 09BF8h R/W Crcerrs 04000h R CRC Error CountAlignment Error Count Algnerrc 04004h RSymerrs 04008h R Symbol Error CountRX Error Count Rxerrc 0400Ch RMPC 04010h R Missed Packets CountSingle Collision Count SCC 04014h REcol 04018h R Excessive Collisions CountMultiple Collision Count MCC 0401Ch RLatecol 04020h R Late Collisions CountCollision Count Colc 04028h RDC 04030h R Defer CountTransmit with No CRS Tncrs 04034h RSEC 04038h R Sequence Error CountCarrier Extension Error Count Cexterr 0403Ch RRlec 04040h R Receive Length Error CountXON Received Count Xonrxc 04048h RXoff Received Count XON Transmitted CountXoff Transmitted Count Fcruc 04058h R FC Received Unsupported CountPackets Received 64 Bytes Count PRC64 0405Ch RPRC127 04060h R Packets Received 65-127 Bytes CountPackets Received 128-255 Bytes Count PRC255 04064h RPRC511 04068h R Packets Received 256-511 Bytes CountPackets Received 512-1023 Bytes Count PRC1023 0406Ch RPRC1522 04070h R Packets Received 1024 to Max Bytes CountGood Packets Received Count Gprc 04074h RBprc 04078h R Broadcast Packets Received CountMulticast Packets Received Count Mprc 0407Ch RGptc 04080h R Good Packets Transmitted CountGood Octets Received Count Gorcl 04088h R/GORCH 0408Ch RGotcl 04090h R/ Gotch 04094 R Good Octets Transmitted CountReceive No Buffers Count Rnbc 040A0h RRUC 040A4h R Receive Undersize CountReceive Fragment Count RFC 040A8h RROC 040ACh R Receive Oversize CountReceive Jabber Count RJC 040B0h RMgtprc 040B4h R Management Packets Received Count1129. RJC Register Bit Description Management Pkts Transmitted Count1 Management Packets Dropped Count1Total Octets Received 130. Torl and Torh Register Bit Descriptions Total Octets TransmittedTotl 040C8h R/W / Toth 040CCh R 131. Totl and Toth Register Bit DescriptionsTPR 040D0h R Total Packets ReceivedTotal Packets Transmitted TPT 040D4h RPTC64 040D8h R Packets Transmitted 64 Bytes CountPackets Transmitted 65-127 Bytes Count PTC127 040DCh RPTC255 040E0h R Packets Transmitted 128-255 Bytes CountPackets Transmitted 256-511 Bytes Count PTC511 040E4h RPTC1023 040E8h R Packets Transmitted 512-1023 Bytes CountPackets Transmitted 1024 Bytes or Greater Count PTC1522 040ECh RMptc 040F0h R Multicast Packets Transmitted CountBroadcast Packets Transmitted Count Bptc 040F4h RTsctc 040F8h R TCP Segmentation Context Transmitted CountTCP Segmentation Context Transmit Fail Count Tsctfc 040FCh RReceive Data Fifo Tail Register Diagnostics RegistersReceive Data Fifo Head Register Rdfh 02410h R/WRdfhs 02420h R/W Receive Data Fifo Head Saved RegisterReceive Data Fifo Tail Saved Register Rdfts 02428h R/WRdfpc 02430h R/W Receive Data Fifo Packet CountTransmit Data Fifo Head Register Tdfh 03410h R/WTdft 03418h R/W Transmit Data Fifo Tail RegisterTransmit Data Fifo Head Saved Register Tdfhs 03420h R/WTdfts 03428h R/W Transmit Data Fifo Tail Saved RegisterTransmit Data Fifo Packet Count Tdfpc 03430h R/W151. Tdfpc Register Bit Description Packet Buffer MemoryPBM 10000h 1FFFCh R/W 152. PBM Bit Description370 Power Up State General ConfigurationGeneral Initialization and Reset Operation Receive InitializationTransmit Initialization Fiber Copper 82544GC/EI Ipgt IPGR1 IPGR2Signal Descriptions Signal Ball Name and FunctionReceive Data Signal InterfaceCarrier Sense Receive ClockSignal Function Pin Gmii 1000 Mbps Operations GMII/MII Features not SupportedSignal Functions MII 10/100 Mbps DifferencesSignal Functions Not Supported Avoiding Gmii Test Modes MAC ConfigurationDirect PHY Indications to MAC Link Setup CTRL.FDPHY Initialization 10/100/1000 Mb/s Copper Media CTRL.RFCEReset Operation Lanpwrgood382 Software Developer’s Manual 383 Initialization of Statistics Fifo Data DiagnosticsFifo State LoopbackTestability Internal LoopbackIdcode Instruction Extest InstructionSAMPLE/PRELOAD Instruction Bypass Instruction388 New Features Appendix Changes From 82544EI/82544GCRegister Offset Register ChangesTable A-1. Register Changes EEC82540EP/EM Differences Serial Flash InterfaceSingle-Port Functionality No TBI/Internal SerDes Interface4 32-Bit PCI Support
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