Intel Intel Gigabit Ethernet Controllers, PCI-X manual 258

Page 272

Register Descriptions

Table 13-28. 1000BASE-T Control Register Bit Description

Bit(s)

Field

 

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

 

 

 

000b

= Normal Mode.

 

 

 

 

 

001b

= Test Mode 1 - Transmit

 

 

 

 

 

Waveform Test.

 

 

 

 

 

010b

= Test Mode 2 - Transmit Jitter

 

 

 

15:13

Test mode

Test (MASTER mode).

R/W

000b

000b

011b = Test Mode 3 - Transmit Jitter

 

 

 

 

 

 

 

Test (SLAVE mode).

 

 

 

 

 

100b

= Test Mode 4 - Transmit

 

 

 

 

 

Distortion Test.

 

 

 

101b, 110b, 111b = Reserved.

1.For the 82541xx and 82547GI/EI, only when PHY register 9, bit 12 is set to a logical 0.

2.0b for the 82541xx and 82547GI/EI only

3.For the 82541xx and 82547GI/EI, only when PHY register 9, bit 12 is set to a logical 1.

NOTES:

1.Values programmed in bits 12:8 of the 1000BASE-T Control Register have no effect unless Auto-Negotiation is restarted (PHY Control Register, bit 9) or the link goes down. These bits can also be overridden by the PHY Control Register.

2.The symbol “!” is equivalent to logical “not.”

3.For the 82541xx and 82547GI/EI, the default for bit 9 is affected by configuration bits in the EEPROM. If EEPROM ANI1000DIS is asserted, then the default is set to 0b. If EEPROM ADV10LU is asserted, then the default is set to 0b.

13.4.7.1.111000BASE-T Status Register

GSTATUS (10d; R)

Table 14-29. 1000BASE-T Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

Idle Error Count

7:0

Idle Error Counter.

RO,

0000b

0000b

The counter stops at 1111b 1111b and

SC

0000b

0000b

 

 

does not roll over.

 

 

 

 

 

 

 

 

 

 

 

Reserved

9:8

Reserved. Should be set to 00b

RO

00b

00b

 

 

 

 

 

 

 

 

1b = Link Partner is capable of

 

 

 

Link Partner

 

1000BASE-T half duplex.

 

 

 

 

0b = Link Partner is not capable of

 

 

 

1000BASE-T

10

RO

0b

0b

1000BASE-T half duplex.

Half Duplex

 

Values in bits 11:10 are not valid until

 

 

 

Capability

 

 

 

 

 

the ANE Register Page Received bit

 

 

 

 

 

 

 

 

 

 

equals 1b.

 

 

 

 

 

 

 

 

 

 

 

1b = Link Partner is capable of

 

 

 

Link Partner

 

1000BASE-T full duplex.

 

 

 

 

0b = Link Partner is not capable of

 

 

 

1000BASE-T

11

1000BASE-T full duplex.

RO

0b

0b

Full Duplex Capability

 

Values in bits 11:10 are not valid until

 

 

 

 

 

the ANE Register Page Received bit

 

 

 

 

 

equals 1b.

 

 

 

 

 

 

 

 

 

Remote Receiver

12

1b = Remote Receiver OK.

RO

0b

0b

Status

0 b = Remote Receiver Not OK.

 

 

 

 

 

 

 

 

 

 

258

Software Developer’s Manual

Page 271 Page 273
Image 272
Page 271 Page 273
Contents 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, Software Developer’s Manual Date Version Comments Initial Public ReleaseSoftware Developer’s Manual Contents TCP Segmentation Use of Multiple Data Descriptors Software Developer’s Manual Vii Power Management 129 Introduction to Power Management 10.1.3 203 13.4.25 13.7.10 Appendix 82540EP/EM and 82545GM/EM Differences Xiv Scope OverviewEthernet Controller Features PCI FeaturesCSA Features 82547GI/EI Only Network Side FeaturesHost Offloading Features Additional Performance Features Additional Ethernet Controller Features Technology FeaturesConventions Related DocumentsMemory Alignment Terminology Register and Bit ReferencesArchitectural Overview IntroductionLAN a LAN B External ArchitecturePHY AGC, A/D Eeprom FlashECHO, Next Fext Microarchitecture 1 PCI/PCI-X Core Interface2 82547GI/EI CSA Interface DMA Engine and Data Fifo4 10/100/1000 Mb/s Receive and Transmit MAC Blocks 5 MII/GMII/TBI/Internal SerDes Interface Block6 10/100/1000 Ethernet Transceiver PHY Eeprom InterfaceDMA Addressing Flash Memory InterfaceExample 2-1. Byte Ordering Little Endian Data OrderingIA Byte # LSB MSB Ethernet AddressingIntel Architecture Byte Ordering Interrupts Hardware Acceleration Capability Buffer and Descriptor StructureChecksum Offloading TCP SegmentationArchitectural Overview Packet Address Filtering IntroductionPacket Reception Receive Descriptor Rdesc Layout Receive Data StorageReceive Descriptor Format Receive Descriptor Status Field Receive Status RDESC.STATUS LayoutPIF Ipcs Tcpcs RSV Ixsm EOP ReceiveReceive Descriptor Errors Field Receive Errors RDESC.ERRORS Layout RXE IPE Tcpe RSVRSV SEQ CXEReceive Descriptor Special Field Special Descriptor Field LayoutPRI CFI Vlan PRIReceive Descriptor Fetching Receive Descriptor Fetching AlgorithmReceive Descriptor Write-Back Receive Descriptor Queue StructureReceive Descriptor Packing Null Descriptor PaddingReceive Descriptor Ring Structure Receive Interrupts Receive Timer InterruptReceive Interrupt Delay Timer / Packet Timer Rdtr Receive Interrupt Absolute Delay Timer Radv Packet Delay Timer Operation State DiagramSmall Receive Packet Detect 8 82544GC/EI Receive Interrupts Receive Packet Checksum OffloadingReceive Descriptor Minimum Threshold ICR.RXDMT Receiver Fifo OverrunSupported Receive Checksum Capabilities Packet Type HW IP Checksum HW TCP/UDP Checksum CalculationMAC Address Filter GC/EI Supported Receive Checksum CapabilitiesPacket Type HW IP Checksum HW TCP/UDP Checksum Packet Type HW IP ChecksumPacket Transmission SNAP/VLAN Filter9.3 IPv4 Filter 9.4 IPv6 FilterTransmit Data Storage Transmit DescriptorsTransmit Descriptor Tdesc Layout Legacy Mode Legacy Transmit Descriptor FormatTransmit Descriptor Tdesc Layout Transmit Descriptor Legacy DescriptionsTransmit Descriptor Description Legacy CMDSTA CSSTransmit Descriptor Command Field Format 10. Transmit Command TDESC.CMD LayoutIDE VLE Dext RSV Ifcs EOPTransmit Descriptor Status Field Format 11. Transmit Status LayoutTransmit Descriptor Special Field Format 12. Special Field TDESC.SPECIAL Layout5 TCP/IP Context Transmit Descriptor Format 6 TCP/IP Context Descriptor Layout 13. Transmit Descriptor Tdesc Layout Type = 0000b14. Transmit Descriptor Tdesc Layout Transmit Description Descriptor Offload6.1 TCP/UDP Offload Transmit Descriptor Command Field Transmit DescriptionTucmd Dtyp82544GC/EI only 15. Command Field TDESC.TUCMD LayoutIDE RSV Dext TSE TCP 16. Transmit Status Layout 7 TCP/IP Data Descriptor Format6.2 TCP/UDP Offload Transmit Descriptor Status Field Popts 17. Transmit Descriptor Tdesc Layout Type = 0001bPopts RSV STA Dcmd Dtyp Dtalen 7.1 TCP/IP Data Descriptor Command Field 18. Command Field TDESC.DCMD LayoutIDE VLE Dext TSE Ifcs EOPReserved 7.2 TCP/IP Data Descriptor Status Field19. Transmit Status Layout 7.3 TCP/IP Data Descriptor Option Field 7.4 TCP/IP Data Descriptor Special Field20. Packet Options Field TDESC.POPTS Layout RSV Txsm IxsmTransmit Descriptor Ring Structure 21. Special Field TDESC.SPECIAL LayoutTransmit Descriptor Ring Structure Transmit Descriptor Fetching Transmit Descriptor Write-backTransmit Interrupts Delayed Transmit Interrupts Assumptions Transmission ProcessTCP Segmentation Performance Packet FormatTCP Segmentation Data Fetch Control TCP/UDP Data FCSTCP Segmentation Indication 3936TCP Segmentation Use of Multiple Data Descriptors TCP Partial Pseudo-Header ChecksumOptions IP and TCP/UDP HeadersVersion IP Hdr Offset High Header Checksum Type of service Version IP Hdr Length FragmentFragment Offset Low Destination Port Sequence Number TCP HeaderLength Checksum Urgent Pointer Options Byte1 Byte0 Destination PortSource Port Destination Port Length Checksum Byte3 Byte2 Byte1 Byte017. UDP Pseudo Header Diagram for IPv4 Transmit Checksum Offloading with TCP Segmentation9 IP/TCP/UDP Header Updating 19. Overall Data Flow 9.1 TCP/IP/UDP Header for the First Frame 9.2 TCP/IP/UDP Header for the Subsequent FramesIP/TCP/UDP Transmit Checksum Offloading 9.3 TCP/IP/UDP Header for the Last FrameIpcss Receive and Transmit Description PCI Configuration Mandatory PCI RegistersAddress Description PCISpecification Update for the latest stepping information Base Address Registers AddrAll base address registers have the following fields Field Bits Read Initial Description Write ValueExpansion ROM Base Address Offset SpaceCapabilities Linked List Address Next PointerPCI definition for more details Bits Initial Value DescriptionStatus Register Layout 82547GI/EIPCI-X Configuration Registers PCI-X Capability IDNext Capability Byte OffsetPCI-X Command Bits Read InitialWrite Value Maximum Memory Read Byte Count. This register setsBits Read Intial Description Write Value PCI-X StatusUSC SCD Command Register as follows Reserved and Undefined AddressesMessage Signaled Interrupts1 Message Signaled Interrupt Configuration RegistersMSI Capability ID Bits Read Initial Description Write Value 05hMessage Control Commands 3.1.4 Message Address3.1.5 Message Upper Address 3.1.6Accepted PCI/PCI-X Command as a Target PCI Commands Abr PCI-X CommandsTransaction Target PCI Commands PCI-X Commands Transaction Cause PCI Commands PCI-X CommandsPCI/PCI-X Command Usage Memory Write OperationsMaster Write Command Usage Algorithm MWI BurstsPCI-X Command Usage Memory Read OperationsMW Bursts Rules for Memory Read OperationsCache Line Information1 Outstanding Memory ReadTarget Transaction Termination LAN DisableInterrupt Assignment 82547GI/EI Only CardBus Application 82541PI/GI/EI Only Eeprom Interface General OverviewStepping Vendor ID Device ID Description Component Identification Via Programming InterfaceComponent Identification Eeprom Device and Interface Software Access Signature and CRC FieldsEeupdate Utility Command Line ParametersEeprom Address Map1 Ethernet Controller Address MapWord Used Bit Image For the 82541xx and 82547GILAN a 82545GM 82540EP82541xx and 82547GI/EI only 82546GB/EB only82541xx 82545GM82540EP/EM ASFAddress Hi Byte Low Byte Word Description Default HW AccessGC/EI and 82541ER Eeprom Address Map Ethernet Address Words 00h-02h Software Compatibility Word Word 03hSoftware Compatibility Word Word 03h Bit Name DescriptionSerDes Configuration Word 04h Eeprom Image Version Word 05hCompatibility Fields Word 05h 07h PBA Number Word 08h, 09hInitialization Control Word 1 Word 0Ah Initialization Control Word 1 Word 0AhSubsystem ID Word 0Bh Subsystem Vendor ID Word 0ChDevice ID Word 0Dh, 11h1 Vendor ID Word 0EhInitialization Control Word 2 Word 0Fh Initialization Control Word 2 Word 0Fh82541PI/GI Only Common Power Word 12h Software Defined Pins Control Word 10h1, 20hPHY Register Address Data Words 10h, 11h, and 13h 1Eh OEM Reserved Words Words 10h, 11h, 13h 1FhSoftware Defined Pins Control Word 10h, 20h Bit Description Default CSA Port Configuration 2 Word 21hCSA Port Configuration 2 Word 21h 20 D0 Power Word 22h high byte 21 D3 Power Word 22h low byteCircuit Control Word 21h Reserved Words 23h 2Eh82541PI/GI/EI and 82547GI/EI Only 10. Initial Management Control Register SettingsManagement Control Word 13h1, 23h2 SMBus Slave Address Word 14h1 low byte, 24h low byte 11. SMBus Slave AddressInitialization Control 3 Word 14h1 high byte, 24h high byte 12. Initialization Control82546GB/EB uses INTB# For Address 24h High Byte / LAN aLED Configuration Defaults Word 2Fh2 Boot Agent Main Setup Options Word 30h27 IPv4 Address Words 15h 16h1 and 25h 26h 28 IPv6 Address words 17h 1Eh1 and 27h 2Eh15. Boot Agent Main Setup Options BBS Boot Agent Configuration Customization Options Word 31hDBS 16. Boot Agent Configuration Customization Options Word 31h SIGMode DFUBoot Agent Configuration Customization Options Word 32h 17. Boot Agent Configuration Customization Options Word 32h18. IBA Capabilities IBA Secondary Port Configuration Words 34h-35hIBA Capabilities Word 33h 19. WOL Mode and Functionality Word 0Ah 20. WOL Mode and Functionality Word 20hChecksum Word Calculation Word 3Fh Eeprom ImagesParallel Flash Memory 21. Flash Memory ManufacturersManufacturer Number124 Flash Control and Accesses Flash Interface OperationRead Accesses Write AccessesFlash Buffer Write Cycle 128 Introduction to Power Management AssumptionsPower States D3cold supportDr State 1.2 D0u State1.4 D3 Timing1.3 D0a D0 active Power Up Off to Dr to D0u to D0a Diagram #Transition From D0a to D3 and Back Without PCI Reset Transition from D0a to D3 and Back Without PCI ResetTransition From D0a to D3 and Back with PCI Reset RST#PCI Reset Without Transition to D3 PCI Reset SequencePCI Power Management Registers Bits Default DescriptionCapability ID Byte Offset = 0 RO Next Item Pointer Byte Offset = 1 ROEeprom Power Management Capabilities PMC 2 Bytes Offset = 2 ROReserved Software Developer’s Manual 139 Pmcsrbse Bridge Support Extensions 3.6 Data RegisterByte Offset = 6 RO Byte Offset = 7 ROAdvanced Power Management Wakeup WakeupAcpi Power Management Wakeup Directed Exact Packet Wakeup PacketsPre-Defined Filters 3.1.3 Broadcast Directed Multicast Packet3.1.4 Magic Packet*1 Offset Field Value Action CommentOffset Field Value Action Comment Bytes 3.1.5 ARP/IPv4 Request Packet1 + S a+ D + S a ARPDirected IPv4 Packet1 Offset # of bytes Field Value Action CommentDirected IPv6 Packet1 IPX Diagnostic Responder Request Packet Example1 Flexible Filter+ S + D + SDirected IPX Packet Example 3.4 IPv6 Neighbor Discovery Filter1Wakeup Packet Storage CRC152 Ethernet Interface Link Interfaces OverviewInternal SerDes Interface/TBI Mode- 1Gb/s1 1.2 8B10B Encoding/DecodingGmii 1 Gb/s Code Groups and Ordered SetsCode Group and Ordered Set Usage Code OrderedSetMII 10/100 Mb/s Internal Interface1Duplex Operation Full Duplex Half DuplexCarrier Extension 1000 Mb/s Only Packet BurstingAuto-Negotiation and Link Setup1 Auto-Negotiation and Link Setup2Auto-Negotiation Link Configuration in Internal Serdes/TBI Mode1Link Speed TXCW.txConfigWord Hardware Auto-NegotiationSoftware Auto-Negotiation Bit DescriptionInternal GMII/MII Mode Forcing LinkUsing Auto-Speed Detection ASD Forcing SpeedAutomatic Detection of Link Speed using SPD-IND DuplexMII Management Registers Comments Regarding Forcing LinkInternal SerDes Mode1 Control Bit Resolution Internal Serdes Mode1 Hardware EnabledInternal Serdes1 Mode Software Enabled Control Bit Effect on Control BitsInternal Serdes Mode1 Auto-Negotiation Skipped Internal PHY Mode Control Bit ResolutionGMII/MII Mode PHY Speed Indication GMII/MII Mode Auto-Speed Detection GMII/MII Mode Force SpeedLoss of Signal/Link Status Indication Internal Serdes ModeInternal PHY Mode GMII/MII Mode Force Link10/100 Mb/s Specific Performance Enhancements Adaptive IFS1Flow Control MAC Control Frames & Reception of Flow Control Packets10. Flow Control Registers Register Name Description3x MAC Control Frame Format Discard Pause Frames and Pass MAC Control Frames Transmission of Pause FramesSoftware Initiated Pause Frame Transmission External Control of Flow Control Operation1802.1q Vlan Packet Format 1 802.1q Tagged FramesVlan Packet Format Comparison Packet #OctetsTransmitting and Receiving 802.1q Packets 802.1q Vlan Packet FilteringAdding 802.1q Tags on Transmits Stripping 802.1q Tags on ReceivesPacket Reception Decision Table VFE178 Configurable LED Outputs1 Selecting an LED Output SourcePolarity Inversion Blink ControlBlink Control 182 PHY Functionality and Features Auto-NegotiationRegister Update Next Page Exchanges11.2 MDI/MDI-X Crossover copper only StatusPin 1000BASE-TPolarity Correction copper only 11.2.2 10/100 Downshift 82540EP/EM OnlyLink Down Energy Detect copper only PHY Power Management copper onlyCable Length Detection copper only 11.4.2 D3 State, No Link Required copper only 11.4.3 D3 Link-Up, Speed-Management Enabled copper only11.4.4 D3 Link-Up, Speed-Management Disabled copper only Mdio Control Mode InitializationDetermining Link State Overview of Link EstablishmentConfiguration Result False LinkForced Operation Determining Duplex State Via Parallel DetectionLink Criteria Auto NegotiationParallel Detection 11.7.1 1000BASE-TUsing SmartSpeed Link Enhancements11.7.3 10BASE-T SmartSpeedLow Power Operation Pause And Asymmetric Pause SettingsAsmdir Settings Pause Setting Management Data Interface11.11 1000 Mbps Operation Powerdown via the PHY RegisterSmart Power-Down DSP ECHO, Next 4DPAM5 Transmit Functions Transmit FifoSpectral Shaper Low-Pass FilterLine Driver Transmit/Receive FlowReceive Functions 11.12 100 Mbps Operation 11.13 10 Mbps OperationDescrambler Viterbi Decoder/Decision Feedback Equalizer DFEPHY Line Length Indication 202 12.2.1 PCI/PCI-X interface Features of Each MACIntroduction1 204 IO BAR MAC Configuration Register Space12.2.3 SDP, LED, INT# output Eeprom Arbitration Shared EepromEeprom Map Flash Access Contention Shared FlashValues Sampled on Reset Pin sampled LAN device controlled Enable/DisableInterrupt Use Power ReportingMulti-Function Advertisement Enabled SummaryInterrupt Line Used INTA#Register Descriptions Register ConventionsMemory-Mapped Access to Internal Registers and Memories Memory-Mapped Access to FlashMemory-Mapped Access to Expansion ROM Memory and I/O Address DecodingIoaddr IodataOffset Abbreviation Name Size IoaddrIodata Register Configurations AD C/BE#30 BitsEthernet Controller Register Summary Category Offset Abbreviation Name82544GC/EI 82547GI/EI onlyIpat 82544GC Xofftxc FcrucPRC64 GprcCategory Abbreviation Name Register82544GC/EI , 82541xx , or 82547GI/EI To the 82544GC/EI , 82541xx , or 82547GIPCI-X Register Access Split1 Ctrl 00000h R/W Main Register DescriptionsDevice Control Register Ctrl Register Bit Description Field Bits Initial Description ValueSpeed SLUIlos Frcdplx SDP0DATASDP1DATA ADVD3WUCField Bits Initial Description BEM = 0 64-bit mode Little-Endian Device Status RegisterStatus 00008h R Little-Endian Data OrderingTbimode Status Register Bit DescriptionTxoff Asdv PCI66Pcixmode PcixspdEEPROM/Flash Control & Data Register Eecd 00010h R/WEecd Register Bit Description 82544GC/EI OnlyEereq EegntEepres EesizeEeprom Read Register Bit Description Eeprom Read Register1Eerd 00014h RW Eeprom Read Register Bit Description 82541xx and 82547GI/EI Done StartFLA 0001Ch R/W Flash Access1Flash Access FLA Extended Device Control Register Ctrlext 00018h, R/W10. Ctrlext Register Bit Description 23 16SDP6IODIR SDP2IODIRSDP7IODIR AsdchkVreg Power 11. GPI to SDP Bit MappingsDown LinkmodeSwdpinshi 12 GC/EI Ctrlext Register Bit DescriptionSwdpiohi CTRL.RST13 GC/EI GPI to SDP Bit Mapping MDI Control Register Mdic 00020h R/W14. MDI Control Register Bit Description RSV PHY REG DataRegadd PhyaddPHY Registers 15. PHY Register Bit Mode DefinitionsRegister Mode Description Field Bits Description Mode HW Rst SW Rst MSB242 Enaxc LSBRO,L Software Developer’s Manual 245 246 For the 82541xx and 82547GI/EI 82544GC/EI only 82541xx Pause82541xx 82547GI/EI 82541xx and 82547GI/EI only 82544GC/EI Only ANEG3ANEG2 RF1Software Developer’s Manual 251 23. Link Partner Ability Register Base Page Bit Description1 82541xx and 82547GI/EI Only 24. PHY Link Page Ability Bit Description110BASE-T 100BASE-TX1b 82541xx Software Developer’s Manual 255 Bits Field Description Mode HW Rst SW Rst Master ANEG0MASTER/SLAVE ANEG1258 Software Developer’s Manual 259 DIS NLP Preen SFDSoftware Developer’s Manual 263 264 Software Developer’s Manual 265 266 82541EI/82547GI B0 stepping 82541/GI/ER and 82547GI B1268 HCD NOK Software Developer’s Manual 271 272 Field Bits Description Mode HW Rst Ledactled SPEED100LED SPEED1000LED276 Software Developer’s Manual 277 To Perform Operation MDI Read/Write Sequence Documented MDI Register 30 Operations151. MDI Register 30 Operations Flow Control Address Low Flow Control Address HighFcal 00028h R/W Fcah 0002Ch R/WFlow Control Type Vlan Ether TypeFCT 00030h R/W VET 00038h R/WFlow Control Transmit Timer Value Fcttv 00170h R/W56. VET Register Bit Description 57. Fcttv Register Bit Description58. Txcw Register Bit Description Transmit Configuration Word Register1Txcw 00178h R/W Receive Configuration Word Register1 Rxcw 00180h R59. Rxcw Register Bit Description LED Control1 Ledctl 00E00h RWANC LED1 ACTIVITY# LED0 LINKUP#Mode Encodings for LED Outputs1 60. LED Control Bit Description161. Mode Encodings for LED Outputs Mode Pneumonic State / Event IndicatedPacket Buffer Allocation PBA 01000H R/W62. PBA Register Bit Description Field Bits Initial Value Description63. ICR Register Bit Description Interrupt Cause Read RegisterICR 000C0H R RXT0 MdacRxcfg GPISDP6Interval Interrupt Throttling Register1ITR 000C4h R/W 64. ICS Register Bit Description Interrupt Cause Set RegisterICS 000C8h W Interrupt Mask Set/Read Register IMS 000D0h R/W65. IMS Register Bit Description To the 82544GC/EIInterrupt Mask Clear Register IMC 000D8h W66. IMC Register Bit Description Receive Control Register Rctl 00100h R/W67. Rctl Register Bit Description SBPMPE LPELBM RdmtsBAM BsizeVFE CfienSecrc PmcfBsex XON Enable 82544GC/EI , 82541xx , and 82547GI/EI only Flow Control Receive Threshold LowFcrtl 02160h R/W 68. Fcrtl Register Bit Description69. Fcrth Register Bit Description Flow Control Receive Threshold HighFcrth 02168h R/W Receive Descriptor Base Address Low Receive Descriptor Base Address HighRdbal 02800hR/W Rdbah 02804h R/WReceive Descriptor Length Receive Descriptor HeadRdlen 02808h R/W RDH 02810h R/WReceive Delay Timer Register Receive Descriptor TailRDT 02818hR/W Rdtr 02820h R/WReceive Interrupt Absolute Delay Timer1 Radv 0282Ch RWReceive Small Packet Detect Interrupt1 Transmit Control RegisterRsrpd 02C00h R/W Tctl 00400hR/W76. Tctl Register Bit Description ColdPSP TCTL.COLDTransmit IPG Register Tipg 00410R/WRtlc Nrtu77. Tipg Register Bit Description IPGR2 IPGR1 IpgtIPGR2 Adaptive IFS Throttle AITAifs 00458R/W Transmit Descriptor Base Address Low Tdbal 03800h R/W78. Aifs Register Bit Description 79. Tdbal Register Bit DescriptionTransmit Descriptor Base Address High Transmit Descriptor LengthTdbah 03804h R/W Tdlen 03808h R/W82. TDH Register Bit Description Transmit Descriptor HeadTDH 03810h R/W Transmit Interrupt Delay Value Transmit Descriptor TailTDT 03818h R/W Tidv 03820h R/WTX DMA Control 82544GC/EI only Transmit Descriptor ControlTxdmac 03000h R/W Txdctl 03828h R/W86. Txdctl Register Bit Description Lwthresh RSV1 Gran RSV Wthresh Hthresh PthreshTransmit Absolute Interrupt Delay Value1 Tadv 0382Ch RWGran LwthreshTspbp TCP Segmentation Pad And Minimum Threshold Tspmt 03830h RWTspbp Tsmt Software Developer’s Manual 319 Receive Descriptor Control Rxdctl 02828h R/W87. Rxdctl Register Bit Description Wthresh RSV Hthresh PthreshReceive Checksum Control Rxcsum 05000h R/W88. Rxcsum Register Bit Description 3111IPV6OFL IpofldTuofld Filter Registers Multicast Table ArrayMTA1270 05200h-053FCh R/W 89. MTA Register Bit DescriptionDestination Address Receive Address Low Receive Address HighRAL 05400h + 8*n R/W RAH 05404h + 8∗n R/WVlan Filter Table Array1 VFTA1270 05600h 057FCh R/W91. RAH Register Bit Description RAHWakeup Registers Wakeup Control RegisterWUC 05800h R/W 92. VFTA1270 Bit DescriptionWakeup Filter Control Register Wufc 05808h R/WApmpme SPMWakeup Status Register WUS 05810h R330 IP Address Valid Ipav 5838h R/W13.6.5 IPv4 Address IP4AT 05840h 05858h R/W2Address Field Dword # Address Bits Initial Value Description13.6.6 IPv6 Address IP6AT 05880h 0588Ch R/WIPV6ADDR0 Dword # Address Bits Initial Value DescriptionFlexible Filter Length Table Wakeup Packet LengthWakeup Packet Memory 128 Bytes Flexible Filter Mask Table Ffmt 09000h 093F8h R/W LEN0LEN1 LEN2Ffvt 09800h 09BF8h R/W Statistics RegistersFlexible Filter Value Table CRC Error Count Alignment Error CountCrcerrs 04000h R Algnerrc 04004h RSymbol Error Count RX Error CountSymerrs 04008h R Rxerrc 0400Ch RMissed Packets Count Single Collision CountMPC 04010h R SCC 04014h RExcessive Collisions Count Multiple Collision CountEcol 04018h R MCC 0401Ch RLate Collisions Count Collision CountLatecol 04020h R Colc 04028h RDefer Count Transmit with No CRSDC 04030h R Tncrs 04034h RSequence Error Count Carrier Extension Error CountSEC 04038h R Cexterr 0403Ch RReceive Length Error Count XON Received CountRlec 04040h R Xonrxc 04048h RXoff Transmitted Count XON Transmitted CountXoff Received Count FC Received Unsupported Count Packets Received 64 Bytes CountFcruc 04058h R PRC64 0405Ch RPackets Received 65-127 Bytes Count Packets Received 128-255 Bytes CountPRC127 04060h R PRC255 04064h RPackets Received 256-511 Bytes Count Packets Received 512-1023 Bytes CountPRC511 04068h R PRC1023 0406Ch RPackets Received 1024 to Max Bytes Count Good Packets Received CountPRC1522 04070h R Gprc 04074h RBroadcast Packets Received Count Multicast Packets Received CountBprc 04078h R Mprc 0407Ch RGood Packets Transmitted Count Good Octets Received CountGptc 04080h R Gorcl 04088h R/GORCH 0408Ch RGood Octets Transmitted Count Receive No Buffers CountGotcl 04090h R/ Gotch 04094 R Rnbc 040A0h RReceive Undersize Count Receive Fragment CountRUC 040A4h R RFC 040A8h RReceive Oversize Count Receive Jabber CountROC 040ACh R RJC 040B0h R129. RJC Register Bit Description Management Packets Received Count1Mgtprc 040B4h R Total Octets Received Management Packets Dropped Count1Management Pkts Transmitted Count1 Total Octets Transmitted Totl 040C8h R/W / Toth 040CCh R130. Torl and Torh Register Bit Descriptions 131. Totl and Toth Register Bit DescriptionsTotal Packets Received Total Packets TransmittedTPR 040D0h R TPT 040D4h RPackets Transmitted 64 Bytes Count Packets Transmitted 65-127 Bytes CountPTC64 040D8h R PTC127 040DCh RPackets Transmitted 128-255 Bytes Count Packets Transmitted 256-511 Bytes CountPTC255 040E0h R PTC511 040E4h RPackets Transmitted 512-1023 Bytes Count Packets Transmitted 1024 Bytes or Greater CountPTC1023 040E8h R PTC1522 040ECh RMulticast Packets Transmitted Count Broadcast Packets Transmitted CountMptc 040F0h R Bptc 040F4h RTCP Segmentation Context Transmitted Count TCP Segmentation Context Transmit Fail CountTsctc 040F8h R Tsctfc 040FCh RDiagnostics Registers Receive Data Fifo Head RegisterReceive Data Fifo Tail Register Rdfh 02410h R/WReceive Data Fifo Head Saved Register Receive Data Fifo Tail Saved RegisterRdfhs 02420h R/W Rdfts 02428h R/WReceive Data Fifo Packet Count Transmit Data Fifo Head RegisterRdfpc 02430h R/W Tdfh 03410h R/WTransmit Data Fifo Tail Register Transmit Data Fifo Head Saved RegisterTdft 03418h R/W Tdfhs 03420h R/WTransmit Data Fifo Tail Saved Register Transmit Data Fifo Packet CountTdfts 03428h R/W Tdfpc 03430h R/WPacket Buffer Memory PBM 10000h 1FFFCh R/W151. Tdfpc Register Bit Description 152. PBM Bit Description370 Power Up State General ConfigurationGeneral Initialization and Reset Operation Receive InitializationTransmit Initialization Fiber Copper 82544GC/EI Ipgt IPGR1 IPGR2Signal Descriptions Signal Ball Name and FunctionSignal Interface Carrier SenseReceive Data Receive ClockGMII/MII Features not Supported Signal FunctionsSignal Function Pin Gmii 1000 Mbps Operations MII 10/100 Mbps DifferencesDirect PHY Indications to MAC Avoiding Gmii Test Modes MAC ConfigurationSignal Functions Not Supported Link Setup CTRL.FDPHY Initialization 10/100/1000 Mb/s Copper Media CTRL.RFCEReset Operation Lanpwrgood382 Software Developer’s Manual 383 Initialization of Statistics Diagnostics Fifo StateFifo Data LoopbackTestability Internal LoopbackExtest Instruction SAMPLE/PRELOAD InstructionIdcode Instruction Bypass Instruction388 New Features Appendix Changes From 82544EI/82544GCRegister Changes Table A-1. Register ChangesRegister Offset EEC82540EP/EM Differences Serial Flash Interface4 32-Bit PCI Support No TBI/Internal SerDes InterfaceSingle-Port Functionality
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