Intel Intel Gigabit Ethernet Controllers, PCI-X TCP Segmentation Context Transmitted Count

Page 377

Register Descriptions

13.7.53TCP Segmentation Context Transmitted Count

TSCTC (040F8h; R)

This register counts the number of TCP segmentation offload transmissions and increments once the last portion of the TCP segmentation context payload is segmented and loaded as a packet into the Ethernet controller’s on-chip transmit buffer. Note that this is not a measurement of the number of packets sent out (covered by other registers). This register only increments if transmits and TCP Segmentation offload are enabled.

31

0

TSCTC

Field

Bit(s)

Initial

Description

Value

 

 

 

 

 

 

 

TSCTC

31:0

0b

Number of TCP Segmentation contexts transmitted count.

 

 

 

 

13.7.54TCP Segmentation Context Transmit Fail Count

TSCTFC (040FCh; R)

This register counts the number of TCP segmentation offload requests to the hardware that failed to transmit all data in the TCP segmentation context payload. There is no indication by hardware of how much data was successfully transmitted. Only one failure event is logged per TCP segmentation context. Failures can be caused by excessive collisions or PAYLEN errors. This register only increments if transmits are enabled.

31

0

TSCTFC

Field

Bit(s)

Initial

Description

Value

 

 

 

 

 

 

 

TSCTFC

31:0

0b

Number of TCP Segmentation contexts where the Ethernet

controller failed to transmit the entire data payload.

 

 

 

 

 

 

 

Software Developer’s Manual

363

Page 376 Page 378
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Page 376 Page 378
Contents 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, Software Developer’s Manual Initial Public Release Date Version CommentsSoftware Developer’s Manual Contents TCP Segmentation Use of Multiple Data Descriptors Software Developer’s Manual Vii Power Management 129 Introduction to Power Management 10.1.3 203 13.4.25 13.7.10 Appendix 82540EP/EM and 82545GM/EM Differences Xiv Overview ScopePCI Features Ethernet Controller FeaturesCSA Features 82547GI/EI Only Network Side FeaturesHost Offloading Features Additional Performance Features Technology Features Additional Ethernet Controller FeaturesRelated Documents ConventionsMemory Alignment Terminology Register and Bit ReferencesIntroduction Architectural OverviewLAN a LAN B External ArchitecturePHY AGC, A/D Eeprom FlashECHO, Next Fext 1 PCI/PCI-X Core Interface MicroarchitectureDMA Engine and Data Fifo 2 82547GI/EI CSA Interface5 MII/GMII/TBI/Internal SerDes Interface Block 4 10/100/1000 Mb/s Receive and Transmit MAC BlocksEeprom Interface 6 10/100/1000 Ethernet Transceiver PHYFlash Memory Interface DMA AddressingExample 2-1. Byte Ordering Little Endian Data OrderingIA Byte # LSB MSB Ethernet AddressingIntel Architecture Byte Ordering Interrupts Buffer and Descriptor Structure Hardware Acceleration CapabilityChecksum Offloading TCP SegmentationArchitectural Overview Packet Address Filtering IntroductionPacket Reception Receive Descriptor Rdesc Layout Receive Data StorageReceive Descriptor Format Receive Status RDESC.STATUS Layout Receive Descriptor Status FieldPIF Ipcs Tcpcs RSV Ixsm EOP ReceiveReceive Descriptor Errors Field RXE IPE Tcpe RSV Receive Errors RDESC.ERRORS LayoutRSV SEQ CXESpecial Descriptor Field Layout Receive Descriptor Special FieldPRI CFI Vlan PRIReceive Descriptor Fetching Algorithm Receive Descriptor FetchingReceive Descriptor Queue Structure Receive Descriptor Write-BackReceive Descriptor Packing Null Descriptor PaddingReceive Descriptor Ring Structure Receive Interrupts Receive Timer InterruptReceive Interrupt Delay Timer / Packet Timer Rdtr Packet Delay Timer Operation State Diagram Receive Interrupt Absolute Delay Timer RadvSmall Receive Packet Detect Receive Packet Checksum Offloading 8 82544GC/EI Receive InterruptsReceive Descriptor Minimum Threshold ICR.RXDMT Receiver Fifo OverrunPacket Type HW IP Checksum HW TCP/UDP Checksum Calculation Supported Receive Checksum CapabilitiesGC/EI Supported Receive Checksum Capabilities MAC Address FilterPacket Type HW IP Checksum HW TCP/UDP Checksum Packet Type HW IP ChecksumSNAP/VLAN Filter Packet Transmission9.3 IPv4 Filter 9.4 IPv6 FilterTransmit Descriptors Transmit Data StorageLegacy Transmit Descriptor Format Transmit Descriptor Tdesc Layout Legacy ModeTransmit Descriptor Tdesc Layout Transmit Descriptor Legacy DescriptionsCMD Transmit Descriptor Description LegacySTA CSS10. Transmit Command TDESC.CMD Layout Transmit Descriptor Command Field FormatIDE VLE Dext RSV Ifcs EOP11. Transmit Status Layout Transmit Descriptor Status Field Format12. Special Field TDESC.SPECIAL Layout Transmit Descriptor Special Field Format5 TCP/IP Context Transmit Descriptor Format 13. Transmit Descriptor Tdesc Layout Type = 0000b 6 TCP/IP Context Descriptor LayoutTransmit Description Descriptor Offload 14. Transmit Descriptor Tdesc LayoutTransmit Description 6.1 TCP/UDP Offload Transmit Descriptor Command FieldTucmd Dtyp82544GC/EI only 15. Command Field TDESC.TUCMD LayoutIDE RSV Dext TSE TCP 16. Transmit Status Layout 7 TCP/IP Data Descriptor Format6.2 TCP/UDP Offload Transmit Descriptor Status Field Popts 17. Transmit Descriptor Tdesc Layout Type = 0001bPopts RSV STA Dcmd Dtyp Dtalen 18. Command Field TDESC.DCMD Layout 7.1 TCP/IP Data Descriptor Command FieldIDE VLE Dext TSE Ifcs EOPReserved 7.2 TCP/IP Data Descriptor Status Field19. Transmit Status Layout 7.4 TCP/IP Data Descriptor Special Field 7.3 TCP/IP Data Descriptor Option Field20. Packet Options Field TDESC.POPTS Layout RSV Txsm Ixsm21. Special Field TDESC.SPECIAL Layout Transmit Descriptor Ring StructureTransmit Descriptor Ring Structure Transmit Descriptor Write-back Transmit Descriptor FetchingTransmit Interrupts Delayed Transmit Interrupts Transmission Process AssumptionsPacket Format TCP Segmentation PerformanceTCP Segmentation Data Fetch Control TCP/UDP Data FCS3936 TCP Segmentation IndicationTCP Partial Pseudo-Header Checksum TCP Segmentation Use of Multiple Data DescriptorsOptions IP and TCP/UDP HeadersVersion IP Hdr Offset High Header Checksum Type of service Version IP Hdr Length FragmentFragment Offset Low TCP Header Destination Port Sequence NumberLength Checksum Urgent Pointer Options Byte1 Byte0 Destination PortByte3 Byte2 Byte1 Byte0 Source Port Destination Port Length ChecksumTransmit Checksum Offloading with TCP Segmentation 17. UDP Pseudo Header Diagram for IPv49 IP/TCP/UDP Header Updating 19. Overall Data Flow 9.2 TCP/IP/UDP Header for the Subsequent Frames 9.1 TCP/IP/UDP Header for the First Frame9.3 TCP/IP/UDP Header for the Last Frame IP/TCP/UDP Transmit Checksum OffloadingIpcss Receive and Transmit Description Mandatory PCI Registers PCI ConfigurationAddress Description PCISpecification Update for the latest stepping information Addr Base Address RegistersField Bits Read Initial Description Write Value All base address registers have the following fieldsOffset Space Expansion ROM Base AddressAddress Next Pointer Capabilities Linked ListBits Initial Value Description PCI definition for more details82547GI/EI Status Register LayoutPCI-X Capability ID PCI-X Configuration RegistersNext Capability Byte OffsetBits Read Initial PCI-X CommandWrite Value Maximum Memory Read Byte Count. This register setsBits Read Intial Description Write Value PCI-X StatusUSC SCD Reserved and Undefined Addresses Command Register as followsMessage Signaled Interrupt Configuration Registers Message Signaled Interrupts1MSI Capability ID Bits Read Initial Description Write Value 05hMessage Control 3.1.4 Message Address Commands3.1.5 Message Upper Address 3.1.6PCI Commands Abr PCI-X Commands Accepted PCI/PCI-X Command as a TargetTransaction Target PCI Commands PCI-X Commands Transaction Cause PCI Commands PCI-X CommandsMemory Write Operations PCI/PCI-X Command UsageMWI Bursts Master Write Command Usage AlgorithmMemory Read Operations PCI-X Command UsageMW Bursts Rules for Memory Read OperationsOutstanding Memory Read Cache Line Information1Target Transaction Termination LAN DisableInterrupt Assignment 82547GI/EI Only CardBus Application 82541PI/GI/EI Only General Overview Eeprom InterfaceStepping Vendor ID Device ID Description Component Identification Via Programming InterfaceComponent Identification Eeprom Device and Interface Signature and CRC Fields Software AccessCommand Line Parameters Eeupdate UtilityEthernet Controller Address Map Eeprom Address Map1Word Used Bit Image For the 82541xx and 82547GI82545GM 82540EP LAN a82541xx and 82547GI/EI only 82546GB/EB only82545GM 82541xxASF 82540EP/EMAddress Hi Byte Low Byte Word Description Default HW AccessGC/EI and 82541ER Eeprom Address Map Software Compatibility Word Word 03h Ethernet Address Words 00h-02hSoftware Compatibility Word Word 03h Bit Name DescriptionEeprom Image Version Word 05h SerDes Configuration Word 04hCompatibility Fields Word 05h 07h PBA Number Word 08h, 09hInitialization Control Word 1 Word 0Ah Initialization Control Word 1 Word 0AhSubsystem Vendor ID Word 0Ch Subsystem ID Word 0BhVendor ID Word 0Eh Device ID Word 0Dh, 11h1Initialization Control Word 2 Word 0Fh Initialization Control Word 2 Word 0Fh82541PI/GI Only Software Defined Pins Control Word 10h1, 20h Common Power Word 12hPHY Register Address Data Words 10h, 11h, and 13h 1Eh OEM Reserved Words Words 10h, 11h, 13h 1FhSoftware Defined Pins Control Word 10h, 20h Bit Description Default CSA Port Configuration 2 Word 21hCSA Port Configuration 2 Word 21h 21 D3 Power Word 22h low byte 20 D0 Power Word 22h high byteCircuit Control Word 21h Reserved Words 23h 2Eh82541PI/GI/EI and 82547GI/EI Only 10. Initial Management Control Register SettingsManagement Control Word 13h1, 23h2 11. SMBus Slave Address SMBus Slave Address Word 14h1 low byte, 24h low byte12. Initialization Control Initialization Control 3 Word 14h1 high byte, 24h high byte82546GB/EB uses INTB# For Address 24h High Byte / LAN aBoot Agent Main Setup Options Word 30h LED Configuration Defaults Word 2Fh227 IPv4 Address Words 15h 16h1 and 25h 26h 28 IPv6 Address words 17h 1Eh1 and 27h 2Eh15. Boot Agent Main Setup Options BBS Boot Agent Configuration Customization Options Word 31hDBS SIG 16. Boot Agent Configuration Customization Options Word 31hMode DFU17. Boot Agent Configuration Customization Options Word 32h Boot Agent Configuration Customization Options Word 32h18. IBA Capabilities IBA Secondary Port Configuration Words 34h-35hIBA Capabilities Word 33h 20. WOL Mode and Functionality Word 20h 19. WOL Mode and Functionality Word 0AhChecksum Word Calculation Word 3Fh Eeprom Images21. Flash Memory Manufacturers Parallel Flash MemoryManufacturer Number124 Flash Interface Operation Flash Control and AccessesWrite Accesses Read AccessesFlash Buffer Write Cycle 128 Assumptions Introduction to Power ManagementD3cold support Power States1.2 D0u State Dr State1.4 D3 Timing1.3 D0a D0 active Diagram # Power Up Off to Dr to D0u to D0aTransition from D0a to D3 and Back Without PCI Reset Transition From D0a to D3 and Back Without PCI ResetRST# Transition From D0a to D3 and Back with PCI ResetPCI Reset Sequence PCI Reset Without Transition to D3Bits Default Description PCI Power Management RegistersCapability ID Byte Offset = 0 RO Next Item Pointer Byte Offset = 1 ROEeprom Power Management Capabilities PMC 2 Bytes Offset = 2 ROReserved Software Developer’s Manual 139 3.6 Data Register Pmcsrbse Bridge Support ExtensionsByte Offset = 6 RO Byte Offset = 7 ROWakeup Advanced Power Management WakeupAcpi Power Management Wakeup Directed Exact Packet Wakeup PacketsPre-Defined Filters Directed Multicast Packet 3.1.3 Broadcast3.1.4 Magic Packet*1 Offset Field Value Action CommentOffset Field Value Action Comment Bytes + S a 3.1.5 ARP/IPv4 Request Packet1+ D + S a ARPOffset # of bytes Field Value Action Comment Directed IPv4 Packet1Directed IPv6 Packet1 Flexible Filter IPX Diagnostic Responder Request Packet Example1+ S + D + S3.4 IPv6 Neighbor Discovery Filter1 Directed IPX Packet ExampleCRC Wakeup Packet Storage152 Link Interfaces Overview Ethernet Interface1.2 8B10B Encoding/Decoding Internal SerDes Interface/TBI Mode- 1Gb/s1Code Groups and Ordered Sets Gmii 1 Gb/sCode Group and Ordered Set Usage Code OrderedSetMII 10/100 Mb/s Internal Interface1Duplex Operation Half Duplex Full DuplexPacket Bursting Carrier Extension 1000 Mb/s OnlyAuto-Negotiation and Link Setup2 Auto-Negotiation and Link Setup1Auto-Negotiation Link Configuration in Internal Serdes/TBI Mode1Link Speed Hardware Auto-Negotiation TXCW.txConfigWordBit Description Software Auto-NegotiationForcing Link Internal GMII/MII ModeForcing Speed Using Auto-Speed Detection ASDDuplex Automatic Detection of Link Speed using SPD-INDMII Management Registers Comments Regarding Forcing LinkInternal Serdes Mode1 Hardware Enabled Internal SerDes Mode1 Control Bit ResolutionInternal Serdes1 Mode Software Enabled Control Bit Effect on Control BitsInternal Serdes Mode1 Auto-Negotiation Skipped Internal PHY Mode Control Bit ResolutionGMII/MII Mode PHY Speed Indication GMII/MII Mode Force Speed GMII/MII Mode Auto-Speed DetectionInternal Serdes Mode Loss of Signal/Link Status IndicationInternal PHY Mode GMII/MII Mode Force LinkAdaptive IFS1 10/100 Mb/s Specific Performance EnhancementsMAC Control Frames & Reception of Flow Control Packets Flow Control10. Flow Control Registers Register Name Description3x MAC Control Frame Format Transmission of Pause Frames Discard Pause Frames and Pass MAC Control FramesExternal Control of Flow Control Operation1 Software Initiated Pause Frame Transmission1 802.1q Tagged Frames 802.1q Vlan Packet FormatVlan Packet Format Comparison Packet #Octets802.1q Vlan Packet Filtering Transmitting and Receiving 802.1q PacketsAdding 802.1q Tags on Transmits Stripping 802.1q Tags on ReceivesVFE Packet Reception Decision Table178 Selecting an LED Output Source Configurable LED Outputs1Blink Control Polarity InversionBlink Control 182 Auto-Negotiation PHY Functionality and FeaturesNext Page Exchanges Register UpdateStatus 11.2 MDI/MDI-X Crossover copper onlyPin 1000BASE-T11.2.2 10/100 Downshift 82540EP/EM Only Polarity Correction copper onlyLink Down Energy Detect copper only PHY Power Management copper onlyCable Length Detection copper only 11.4.2 D3 State, No Link Required copper only 11.4.3 D3 Link-Up, Speed-Management Enabled copper only11.4.4 D3 Link-Up, Speed-Management Disabled copper only Initialization Mdio Control ModeOverview of Link Establishment Determining Link StateFalse Link Configuration ResultForced Operation Determining Duplex State Via Parallel DetectionAuto Negotiation Link CriteriaParallel Detection 11.7.1 1000BASE-TLink Enhancements Using SmartSpeed11.7.3 10BASE-T SmartSpeedPause And Asymmetric Pause Settings Low Power OperationAsmdir Settings Pause Setting Management Data Interface11.11 1000 Mbps Operation Powerdown via the PHY RegisterSmart Power-Down DSP ECHO, Next 4DPAM5 Transmit Fifo Transmit FunctionsLow-Pass Filter Spectral ShaperLine Driver Transmit/Receive FlowReceive Functions 11.13 10 Mbps Operation 11.12 100 Mbps OperationDescrambler Viterbi Decoder/Decision Feedback Equalizer DFEPHY Line Length Indication 202 12.2.1 PCI/PCI-X interface Features of Each MACIntroduction1 204 IO BAR MAC Configuration Register Space12.2.3 SDP, LED, INT# output Eeprom Arbitration Shared EepromEeprom Map Shared Flash Flash Access ContentionPin sampled LAN device controlled Enable/Disable Values Sampled on ResetInterrupt Use Power ReportingMulti-Function Advertisement Summary EnabledInterrupt Line Used INTA#Register Conventions Register DescriptionsMemory-Mapped Access to Flash Memory-Mapped Access to Internal Registers and MemoriesMemory-Mapped Access to Expansion ROM Memory and I/O Address DecodingIodata IoaddrOffset Abbreviation Name Size IoaddrAD C/BE#30 Bits Iodata Register ConfigurationsCategory Offset Abbreviation Name Ethernet Controller Register Summary82544GC/EI 82547GI/EI onlyIpat 82544GC Fcruc XofftxcPRC64 GprcAbbreviation Name Register Category82544GC/EI , 82541xx , or 82547GI/EI To the 82544GC/EI , 82541xx , or 82547GIPCI-X Register Access Split1 Ctrl 00000h R/W Main Register DescriptionsDevice Control Register Field Bits Initial Description Value Ctrl Register Bit DescriptionSpeed SLUIlos SDP0DATA FrcdplxSDP1DATA ADVD3WUCField Bits Initial Description Device Status Register BEM = 0 64-bit mode Little-EndianStatus 00008h R Little-Endian Data OrderingTbimode Status Register Bit DescriptionTxoff PCI66 AsdvPcixmode PcixspdEecd 00010h R/W EEPROM/Flash Control & Data RegisterEecd Register Bit Description 82544GC/EI OnlyEegnt EereqEepres EesizeEeprom Read Register Bit Description Eeprom Read Register1Eerd 00014h RW Done Start Eeprom Read Register Bit Description 82541xx and 82547GI/EIFLA 0001Ch R/W Flash Access1Flash Access FLA Ctrlext 00018h, R/W Extended Device Control Register10. Ctrlext Register Bit Description 23 16SDP2IODIR SDP6IODIRSDP7IODIR Asdchk11. GPI to SDP Bit Mappings Vreg PowerDown Linkmode12 GC/EI Ctrlext Register Bit Description SwdpinshiSwdpiohi CTRL.RST13 GC/EI GPI to SDP Bit Mapping Mdic 00020h R/W MDI Control RegisterRSV PHY REG Data 14. MDI Control Register Bit DescriptionRegadd PhyaddPHY Registers 15. PHY Register Bit Mode DefinitionsRegister Mode Description MSB Field Bits Description Mode HW Rst SW Rst242 LSB EnaxcRO,L Software Developer’s Manual 245 246 For the 82541xx and 82547GI/EI Pause 82544GC/EI only 82541xx82541xx 82547GI/EI 82541xx and 82547GI/EI only ANEG3 82544GC/EI OnlyANEG2 RF1Software Developer’s Manual 251 23. Link Partner Ability Register Base Page Bit Description1 24. PHY Link Page Ability Bit Description1 82541xx and 82547GI/EI Only10BASE-T 100BASE-TX1b 82541xx Software Developer’s Manual 255 Bits Field Description Mode HW Rst SW Rst ANEG0 MasterMASTER/SLAVE ANEG1258 Software Developer’s Manual 259 DIS NLP SFD PreenSoftware Developer’s Manual 263 264 Software Developer’s Manual 265 266 82541/GI/ER and 82547GI B1 82541EI/82547GI B0 stepping268 HCD NOK Software Developer’s Manual 271 272 Field Bits Description Mode HW Rst Ledactled SPEED1000LED SPEED100LED276 Software Developer’s Manual 277 To Perform Operation MDI Read/Write Sequence Documented MDI Register 30 Operations151. MDI Register 30 Operations Flow Control Address High Flow Control Address LowFcal 00028h R/W Fcah 0002Ch R/WVlan Ether Type Flow Control TypeFCT 00030h R/W VET 00038h R/WFcttv 00170h R/W Flow Control Transmit Timer Value56. VET Register Bit Description 57. Fcttv Register Bit Description58. Txcw Register Bit Description Transmit Configuration Word Register1Txcw 00178h R/W Rxcw 00180h R Receive Configuration Word Register159. Rxcw Register Bit Description Ledctl 00E00h RW LED Control1ANC LED1 ACTIVITY# LED0 LINKUP#60. LED Control Bit Description1 Mode Encodings for LED Outputs1Mode Pneumonic State / Event Indicated 61. Mode Encodings for LED OutputsPBA 01000H R/W Packet Buffer Allocation62. PBA Register Bit Description Field Bits Initial Value Description63. ICR Register Bit Description Interrupt Cause Read RegisterICR 000C0H R Mdac RXT0Rxcfg GPISDP6Interval Interrupt Throttling Register1ITR 000C4h R/W 64. ICS Register Bit Description Interrupt Cause Set RegisterICS 000C8h W IMS 000D0h R/W Interrupt Mask Set/Read Register65. IMS Register Bit Description To the 82544GC/EIIMC 000D8h W Interrupt Mask Clear Register66. IMC Register Bit Description Rctl 00100h R/W Receive Control Register67. Rctl Register Bit Description SBPLPE MPELBM RdmtsBsize BAMVFE CfienSecrc PmcfBsex Flow Control Receive Threshold Low XON Enable 82544GC/EI , 82541xx , and 82547GI/EI onlyFcrtl 02160h R/W 68. Fcrtl Register Bit Description69. Fcrth Register Bit Description Flow Control Receive Threshold HighFcrth 02168h R/W Receive Descriptor Base Address High Receive Descriptor Base Address LowRdbal 02800hR/W Rdbah 02804h R/WReceive Descriptor Head Receive Descriptor LengthRdlen 02808h R/W RDH 02810h R/WReceive Descriptor Tail Receive Delay Timer RegisterRDT 02818hR/W Rdtr 02820h R/WRadv 0282Ch RW Receive Interrupt Absolute Delay Timer1Transmit Control Register Receive Small Packet Detect Interrupt1Rsrpd 02C00h R/W Tctl 00400hR/WCold 76. Tctl Register Bit DescriptionPSP TCTL.COLDTipg 00410R/W Transmit IPG RegisterRtlc NrtuIPGR2 IPGR1 Ipgt 77. Tipg Register Bit DescriptionIPGR2 Adaptive IFS Throttle AITAifs 00458R/W Tdbal 03800h R/W Transmit Descriptor Base Address Low78. Aifs Register Bit Description 79. Tdbal Register Bit DescriptionTransmit Descriptor Length Transmit Descriptor Base Address HighTdbah 03804h R/W Tdlen 03808h R/W82. TDH Register Bit Description Transmit Descriptor HeadTDH 03810h R/W Transmit Descriptor Tail Transmit Interrupt Delay ValueTDT 03818h R/W Tidv 03820h R/WTransmit Descriptor Control TX DMA Control 82544GC/EI onlyTxdmac 03000h R/W Txdctl 03828h R/WLwthresh RSV1 Gran RSV Wthresh Hthresh Pthresh 86. Txdctl Register Bit DescriptionTadv 0382Ch RW Transmit Absolute Interrupt Delay Value1Gran LwthreshTspbp TCP Segmentation Pad And Minimum Threshold Tspmt 03830h RWTspbp Tsmt Software Developer’s Manual 319 Rxdctl 02828h R/W Receive Descriptor Control87. Rxdctl Register Bit Description Wthresh RSV Hthresh PthreshRxcsum 05000h R/W Receive Checksum Control88. Rxcsum Register Bit Description 3111IPV6OFL IpofldTuofld Multicast Table Array Filter RegistersMTA1270 05200h-053FCh R/W 89. MTA Register Bit DescriptionDestination Address Receive Address High Receive Address LowRAL 05400h + 8*n R/W RAH 05404h + 8∗n R/WVFTA1270 05600h 057FCh R/W Vlan Filter Table Array191. RAH Register Bit Description RAHWakeup Control Register Wakeup RegistersWUC 05800h R/W 92. VFTA1270 Bit DescriptionWufc 05808h R/W Wakeup Filter Control RegisterApmpme SPMWUS 05810h R Wakeup Status Register330 Ipav 5838h R/W IP Address ValidIP4AT 05840h 05858h R/W2 13.6.5 IPv4 AddressAddress Field Dword # Address Bits Initial Value DescriptionIP6AT 05880h 0588Ch R/W 13.6.6 IPv6 AddressIPV6ADDR0 Dword # Address Bits Initial Value DescriptionFlexible Filter Length Table Wakeup Packet LengthWakeup Packet Memory 128 Bytes LEN0 Flexible Filter Mask Table Ffmt 09000h 093F8h R/WLEN1 LEN2Ffvt 09800h 09BF8h R/W Statistics RegistersFlexible Filter Value Table Alignment Error Count CRC Error CountCrcerrs 04000h R Algnerrc 04004h RRX Error Count Symbol Error CountSymerrs 04008h R Rxerrc 0400Ch RSingle Collision Count Missed Packets CountMPC 04010h R SCC 04014h RMultiple Collision Count Excessive Collisions CountEcol 04018h R MCC 0401Ch RCollision Count Late Collisions CountLatecol 04020h R Colc 04028h RTransmit with No CRS Defer CountDC 04030h R Tncrs 04034h RCarrier Extension Error Count Sequence Error CountSEC 04038h R Cexterr 0403Ch RXON Received Count Receive Length Error CountRlec 04040h R Xonrxc 04048h RXoff Transmitted Count XON Transmitted CountXoff Received Count Packets Received 64 Bytes Count FC Received Unsupported CountFcruc 04058h R PRC64 0405Ch RPackets Received 128-255 Bytes Count Packets Received 65-127 Bytes CountPRC127 04060h R PRC255 04064h RPackets Received 512-1023 Bytes Count Packets Received 256-511 Bytes CountPRC511 04068h R PRC1023 0406Ch RGood Packets Received Count Packets Received 1024 to Max Bytes CountPRC1522 04070h R Gprc 04074h RMulticast Packets Received Count Broadcast Packets Received CountBprc 04078h R Mprc 0407Ch RGood Octets Received Count Good Packets Transmitted CountGptc 04080h R Gorcl 04088h R/GORCH 0408Ch RReceive No Buffers Count Good Octets Transmitted CountGotcl 04090h R/ Gotch 04094 R Rnbc 040A0h RReceive Fragment Count Receive Undersize CountRUC 040A4h R RFC 040A8h RReceive Jabber Count Receive Oversize CountROC 040ACh R RJC 040B0h R129. RJC Register Bit Description Management Packets Received Count1Mgtprc 040B4h R Total Octets Received Management Packets Dropped Count1Management Pkts Transmitted Count1 Totl 040C8h R/W / Toth 040CCh R Total Octets Transmitted130. Torl and Torh Register Bit Descriptions 131. Totl and Toth Register Bit DescriptionsTotal Packets Transmitted Total Packets ReceivedTPR 040D0h R TPT 040D4h RPackets Transmitted 65-127 Bytes Count Packets Transmitted 64 Bytes CountPTC64 040D8h R PTC127 040DCh RPackets Transmitted 256-511 Bytes Count Packets Transmitted 128-255 Bytes CountPTC255 040E0h R PTC511 040E4h RPackets Transmitted 1024 Bytes or Greater Count Packets Transmitted 512-1023 Bytes CountPTC1023 040E8h R PTC1522 040ECh RBroadcast Packets Transmitted Count Multicast Packets Transmitted CountMptc 040F0h R Bptc 040F4h RTCP Segmentation Context Transmit Fail Count TCP Segmentation Context Transmitted CountTsctc 040F8h R Tsctfc 040FCh RReceive Data Fifo Head Register Diagnostics RegistersReceive Data Fifo Tail Register Rdfh 02410h R/WReceive Data Fifo Tail Saved Register Receive Data Fifo Head Saved RegisterRdfhs 02420h R/W Rdfts 02428h R/WTransmit Data Fifo Head Register Receive Data Fifo Packet CountRdfpc 02430h R/W Tdfh 03410h R/WTransmit Data Fifo Head Saved Register Transmit Data Fifo Tail RegisterTdft 03418h R/W Tdfhs 03420h R/WTransmit Data Fifo Packet Count Transmit Data Fifo Tail Saved RegisterTdfts 03428h R/W Tdfpc 03430h R/WPBM 10000h 1FFFCh R/W Packet Buffer Memory151. Tdfpc Register Bit Description 152. PBM Bit Description370 General Configuration Power Up StateReceive Initialization General Initialization and Reset OperationTransmit Initialization Ipgt IPGR1 IPGR2 Fiber Copper 82544GC/EISignal Ball Name and Function Signal DescriptionsCarrier Sense Signal InterfaceReceive Data Receive ClockSignal Functions GMII/MII Features not SupportedSignal Function Pin Gmii 1000 Mbps Operations MII 10/100 Mbps DifferencesDirect PHY Indications to MAC Avoiding Gmii Test Modes MAC ConfigurationSignal Functions Not Supported CTRL.FD Link SetupCTRL.RFCE PHY Initialization 10/100/1000 Mb/s Copper MediaLanpwrgood Reset Operation382 Software Developer’s Manual 383 Initialization of Statistics Fifo State DiagnosticsFifo Data LoopbackInternal Loopback TestabilitySAMPLE/PRELOAD Instruction Extest InstructionIdcode Instruction Bypass Instruction388 Appendix Changes From 82544EI/82544GC New FeaturesTable A-1. Register Changes Register ChangesRegister Offset EECSerial Flash Interface 82540EP/EM Differences4 32-Bit PCI Support No TBI/Internal SerDes InterfaceSingle-Port Functionality
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