
Installed files - ModelSim EE
| Directory | Files & subdirectories | Description | |
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| ./vhdl_src/synopsys | mti_std_logic_arith.vhd, | sources for | |
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| mti_std_logic_misc.vhd, | rebuilding | |
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| mti_std_logic_signed.vhd | accelerated | |
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| mti_std_logic_unsigned.v | arithmetic packages | |
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| hd, std_logic_textio.vhd, |
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| syn_ari.vhd, |
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| syn_attributes.vhd, |
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| syn_type.vhd |
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| ./vhdl_src/verilog | vltypes.vhd | source for rebuilding | |
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| Verilog library | |
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| ./vhdl_src/vital2.2b | prmtvs_b.vhd, | sources for | |
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| prmtvs_p.vhd, | rebuilding VITAL | |
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| timing_b.vhd, | version 2.2b library | |
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| timing_p.vhd |
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| ./vhdl_src/vital95 | prmtvs_b.vhd, | sources for | |
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| prmtvs_p.vhd, | rebuilding VITAL | |
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| timing_b.vhd, | version 95 library | |
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| timing_p.vhd |
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Note: The version of std_logic_arith contained in file std_arit.vhd is NOT the version that is compiled into the ModelSim ieee library.
This version is compiled into library arithmetic and is available for customers who may have previously used Mentor QuickVhdl, and used the Mentor arithmetic package that contained std_logic_arith modified for use with the Mentor synthesis tools.
The source for the
vhdl_src/synopsys/mti_std_logic_arith.vhd
18Start Here for ModelSim EE