Cypress CY7C1422BV18 manuals
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Cypress CY7C1422BV18 Manual
30 pages 706.53 Kb
36-Mbit DDR-II SIO SRAM 2-Word Burst ArchitectureCY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18Features Configurations Functional Description Selection Guide 2 CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18Logic Block Diagram (CY7C1422BV18) Logic Block Diagram (CY7C1429BV18) 3 CY7C1423BV18, CY7C1424BV18Logic Block Diagram (CY7C1423BV18) Logic Block Diagram (CY7C1424BV18) 4 CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV187 CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV188 CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18Functional OverviewRead Operations Write Operations Byte Write Operations Single Clock Mode DDR Operation Depth Expansion Programmable Impedance 9 CY7C1422BV18, CY7C1429BV18Echo Clocks DLL Application Example 10 Truth TableWrite Cycle Descriptions 12 IEEE 1149.1 Serial Boundary Scan (JTAG)Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Test Data-Out (TDO) Performing a TAP Reset TAP Registers TAP Instruction Set 14 CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV1818 CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18Boundary Scan Order Power Up Sequence in DDR-II SRAM 19 VVPower Up Sequence DLL Constraints / 22 CY7C1422BV18, CY7C1429BV18Capacitance Thermal Resistance 23 CY7C1423BV18, CY7C1424BV18Switching Characteristics 24 CY7C1423BV18, CY7C1424BV1829 CY7C1422BV18, CY7C1429BV18Document #: 001-07035 Rev. *D Page 29 of 30 Package DiagramFigure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195 30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page
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