Cypress CY7C1422BV18, CY7C1423BV18, CY7C1424BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

CY7C1422BV18, CY7C1429BV18
CY7C1423BV18, CY7C1424BV18
Document #: 001-07035 Rev. *D Page 3 of 30
Logic Block Diagram (CY7C1423BV18)
Logic Block Diagram (CY7C1424BV18)
1M x 18 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
LD Q[17:0]
Reg.
Reg.
Reg.
18
36
18
BWS[1:0]
VREF
Write Add. Decode
Write
Data Reg
18 18
20
18
R/W
LD
R/W
CQ
CQ
DOFF
1M x 18 Array
Write
Data Reg
Control
Logic
C
C
18
512K x 36 Array
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
LD Q[35:0]
Reg.
Reg.
Reg.
36
72
36
BWS[3:0]
VREF
Write Add. Decode
Write
Data Reg
36 36
19
36
R/W
LD
R/W
CQ
CQ
DOFF
512K x 36 Array
Write
Data Reg
Control
Logic
C
C
36
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