250 | Cypress CY7C1422BV18, CY7C1423BV18, CY7C1429BV18, CY7C1424BV18

CY7C1422BV18, CY7C1429BV18

CY7C1423BV18, CY7C1424BV18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
250	CY7C1422BV18-250BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1429BV18-250BZC

	CY7C1423BV18-250BZC

	CY7C1424BV18-250BZC

	CY7C1422BV18-250BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1429BV18-250BZXC

	CY7C1423BV18-250BZXC

	CY7C1424BV18-250BZXC

	CY7C1422BV18-250BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1429BV18-250BZI

	CY7C1423BV18-250BZI

	CY7C1424BV18-250BZI

	CY7C1422BV18-250BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1429BV18-250BZXI

	CY7C1423BV18-250BZXI

	CY7C1424BV18-250BZXI

200	CY7C1422BV18-200BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1429BV18-200BZC

	CY7C1423BV18-200BZC

	CY7C1424BV18-200BZC

	CY7C1422BV18-200BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1429BV18-200BZXC

	CY7C1423BV18-200BZXC

	CY7C1424BV18-200BZXC

	CY7C1422BV18-200BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1429BV18-200BZI

	CY7C1423BV18-200BZI

	CY7C1424BV18-200BZI

	CY7C1422BV18-200BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1429BV18-200BZXI

	CY7C1423BV18-200BZXI

	CY7C1424BV18-200BZXI

Document #: 001-07035 Rev. *D

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Cypress CY7C1422BV18, CY7C1423BV18, CY7C1429BV18, CY7C1424BV18 manual 250

Contents

Selection Guide FeaturesConfigurations Functional Description Logic Block Diagram CY7C1422BV18 CLKDoff Logic Block Diagram CY7C1424BV18 Logic Block Diagram CY7C1423BV18 CY7C1429BV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1422BV18 4M x CY7C1424BV18 1M x CY7C1423BV18 2M x Pin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect to Functional Overview Echo Clocks Application Example BWS0/ BWS1 NWS0 NWS1 Truth TableWrite Cycle Descriptions LD R/W BWS0 BWS1 BWS2 BWS3 BWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDI TAP Timing and Test Conditions TAP AC Switching Characteristics Register Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction Codes Bit # Bump ID Boundary Scan Order Power Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max Unit Switching Characteristics HighLOW DLL Timing Static to DLL Reset Switching Waveforms NOP Read WriteBurst Ordering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package Diagram REV ECN no Submission ORIG. Description of Change Date Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History