Contents
Main
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
Features
Configurations
Functional Description
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
Logic Block Diagram (CY7C1422BV18)
Logic Block Diagram (CY7C1429BV18)
A
CY7C1423BV18, CY7C1424BV18
Logic Block Diagram (CY7C1423BV18)
Logic Block Diagram (CY7C1424BV18)
A
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
Pin Configuration
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
Pin Configuration
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
Pin Definitions
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
Pin Definitions
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
Functional Overview
Read Operations
Write Operations
Byte Write Operations
CY7C1422BV18, CY7C1429BV18
Echo Clocks
DLL
Application Example
Truth Table
Write Cycle Descriptions
Page
IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Test Access PortTest Clock
Test Mode Select (TMS)
Test D ata- In (T DI)
Page
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
TAP Controller State Diagram
TAP Controller Block Diagram
TAP Electrical Characteristics
TAP AC Switching Characteristics
TAP Timing and Test Conditions
Identification Register Definitions
Scan Register Sizes
Instruction Codes
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
Boundary Scan Order
Power Up Sequence in DDR-II SRAM
VV
Power Up Sequence
DLL Constraints
/
Maximum Ratings
Operating Range
Electrical Characteristics
DC Electrical Characteristics
AC Electrical Characteristics
Electrical Characteristics
DC Electrical Characteristics
CY7C1422BV18, CY7C1429BV18
Capacitance
Thermal Resistance
CY7C1423BV18, CY7C1424BV18
Switching Characteristics
CY7C1423BV18, CY7C1424BV18
Switching Characteristics
Switching Waveforms
Page
Page
Ordering Information
CY7C1422BV18, CY7C1429BV18
Document #: 001-07035 Rev. *D Page 29 of 30
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Package Diagram
Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195
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