Cypress CY7C1422BV18, CY7C1423BV18, CY7C1424BV18, CY7C1429BV18 CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

CY7C1422BV18, CY7C1429BV18
CY7C1423BV18, CY7C1424BV18
Document #: 001-07035 Rev. *D Page 2 of 30
Logic Block Diagram (CY7C1422BV18)
Logic Block Diagram (CY7C1429BV18)
2M x 8 Array
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
LD Q[7:0]
Reg.
Reg.
Reg.
8
16
8
NWS[1:0]
VREF
Write Add. Decode
Write
Data Reg
88
21
8
R/W
LD
R/W
CQ
CQ
DOFF
2M x 8 Array
Write
Data Reg
Control
Logic
C
C
8
2M x 9 Array
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
LD Q[8:0]
Reg.
Reg.
Reg.
9
18
9
BWS[0]
VREF
Write Add. Decode
Write
Data Reg
99
21
9
R/W
LD
R/W
CQ
CQ
DOFF
2M x 9 Array
Write
Data Reg
Control
Logic
C
C
9
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