Cypress CY7C1576V18 manuals
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Cypress CY7C1576V18 Manual
28 pages 731.53 Kb
72-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18Features Configurations Functional Description Selection GuideDocument Number: 001-05384 Rev. *F Page 2 of 28 2 Logic Block Diagram (CY7C1561V18)Logic Block Diagram (CY7C1576V18) 3 CY7C1563V18, CY7C1565V18Document Number: 001-05384 Rev. *F Page 3 of 28 Logic Block Diagram (CY7C1563V18)Logic Block Diagram (CY7C1565V18) 4 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 5 CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 6 CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V187 CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V188 CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V1815 CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V1818 CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18Boundary Scan Order 19 Power Up Sequence in QDR-II+ SRAMPower Up SequenceClock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) VDD/VDDQ DOFFUnstable Clock > 2048 Stable Clock Start Normal Operation VDD/VDDQ Stable (< + 0.1V DC per 50 ns) 20 Maximum RatingsElectrical Characteristics DC Electrical Characteristics 21 Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics 22 CapacitanceThermal Resistance 23 Switching CharacteristicsDocument Number: 001-05384 Rev. *F Page 24 of 28 Switching Waveforms 24 NOPREADQVLDRead/Write/Deselect Sequence Figure 5. Waveform for 2.5 Cycle Read Latency RPS WPS A D NOP WRITE READ WRITE 123 4 567 8
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