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Cypress CY7C1561V18, CY7C1563V18, CY7C1565V18, CY7C1576V18 Electrical Characteristics

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CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Document Number: 001-05384 Rev. *F Page 21 of 28

IDD [22] VDD Operating Supply VDD = Max,

IOUT = 0 mA,

f = fMAX = 1/tCYC

333 MHz x8 1200 mA

x9 1200

x18 1200

x36 1200

300 MHz x8 1100 mA

x9 1100

x18 1100

x36 1100

ISB1 Automatic Power down

Current Max VDD,

Both Ports Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC, Inputs

Static

400 MHz x8 550 mA

x9 550

x18 550

x36 550

375 MHz x8 525 mA

x9 525

x18 525

x36 525

333 MHz x8 500 mA

x9 500

x18 500

x36 500

300 MHz x8 450 mA

x9 450

x18 450

x36 450

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [15]

Parameter Description Test Conditions Min Typ Max Unit

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Contents

Main 72-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Features Configurations Functional Description Logic Block Diagram (CY7C1561V18) Logic Block Diagram (CY7C1576V18) CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev. *F Page 3 of 28 Logic Block Diagram (CY7C1563V18) Logic Block Diagram (CY7C1565V18) Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Pin Definitions CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 NC NC Pin Definitions CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example Truth Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Page TAP Controller State Diagram CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Boundary Scan Order Power Up Sequence in QDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) VDD/VDDQ DOFF Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Document Number: 001-05384 Rev. *F Page 24 of 28 Switching Waveforms NOPREAD QVLD Read/Write/Deselect Sequence Figure 5. Waveform for 2.5 Cycle Read Latency RPS Page Ordering Information Document Number: 001-05384 Rev. *F Page 27 of 28 Package Diagram [+] Feedback [+] Feedback Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195 51-85195-*A Document History Page