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Cypress CY7C1565V18 VDD Operating Supply VDD = Max 333 MHz, 300 MHz, VIN ≥ VIH or VIN ≤ VIL X18

Models: CY7C1576V18 CY7C1563V18 CY7C1561V18 CY7C1565V18

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CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [15]

Parameter	Description	Test Conditions			Min	Typ	Max	Unit
IDD [22]	VDD Operating Supply	VDD = Max,	333 MHz	x8			1200	mA
		IOUT = 0 mA,
		IOUT = 0 mA,		x9			1200
		f = fMAX = 1/tCYC
		f = fMAX = 1/tCYC		x18			1200
				x18			1200

				x36			1200

			300 MHz	x8			1100	mA

				x9			1100

				x18			1100

				x36			1100

ISB1	Automatic Power down	Max VDD,	400 MHz	x8			550	mA
	Current	Both Ports Deselected,
	Current	Both Ports Deselected,		x9			550
		VIN ≥ VIH or VIN ≤ VIL		x9			550

				x18			550
		f = fMAX = 1/tCYC, Inputs		x18			550
		Static		x36			550

			375 MHz	x8			525	mA

				x9			525

				x18			525

				x36			525

			333 MHz	x8			500	mA

				x9			500

				x18			500

				x36			500

			300 MHz	x8			450	mA

				x9			450

				x18			450

				x36			450

Document Number: 001-05384 Rev. *F

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Cypress CY7C1565V18, CY7C1576V18 VDD Operating Supply VDD = Max 333 MHz, 300 MHz, Automatic Power down Max VDD 400 MHz

Contents

Selection Guide Features ConfigurationsFunctional Description Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Logic Block Diagram CY7C1561V18 Logic Block Diagram CY7C1576V18Doff Logic Block Diagram CY7C1565V18 Logic Block Diagram CY7C1563V18 Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1561V18 8M x CY7C1576V18 8M x CY7C1563V18 4M x WPS BWSCY7C1565V18 2M x Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for Jtag Read Operations Functional OverviewWrite Operations Byte Write Operations Application Example Valid Data Indicator QvldDepth Expansion Programmable Impedance Write Cycle Descriptions Truth TableOperation Comments Write cycle description table for CY7C1565V18 follows Write cycle description table for CY7C1576V18 followsDevice Into the device. D359 remains unaltered Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block Diagram TAP Timing and Test Conditions TAP AC Switching Characteristics Scan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit Size Bit # Bump ID Boundary Scan Order Power Up Sequence in QDR-II+ Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings VDD Operating Supply VDD = Max 333 MHz Automatic Power down Max VDD 400 MHz300 MHz Current Both Ports Deselected Capacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max Unit Consortium Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max High Read/Write/Deselect Sequence 31, 32 Switching Waveforms Ordering Information 333 Ball Fbga 15 x 17 x 1.4 mm Package Diagram Document History