Cypress CY7C1561V18, CY7C1563V18, CY7C1565V18, CY7C1576V18 - page 25

CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Document Number: 001-05384 Rev. *F Page 25 of 28

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

400 CY7C1561V18-400BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-400BZC

CY7C1563V18-400BZC

CY7C1565V18-400BZC

CY7C1561V18-400BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-400BZXC

CY7C1563V18-400BZXC

CY7C1565V18-400BZXC

CY7C1561V18-400BZI 51-85195 165-Ball Fine Pitch Ba ll Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1576V18-400BZI

CY7C1563V18-400BZI

CY7C1565V18-400BZI

CY7C1561V18-400BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-400BZXI

CY7C1563V18-400BZXI

CY7C1565V18-400BZXI

375 CY7C1561V18-375BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-375BZC

CY7C1563V18-375BZC

CY7C1565V18-375BZC

CY7C1561V18-375BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-375BZXC

CY7C1563V18-375BZXC

CY7C1565V18-375BZXC

CY7C1561V18-375BZI 51-85195 165-Ball Fine Pitch Ba ll Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1576V18-375BZI

CY7C1563V18-375BZI

CY7C1565V18-375BZI

CY7C1561V18-375BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-375BZXI

CY7C1563V18-375BZXI

CY7C1565V18-375BZXI

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Contents

Main 72-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Features Configurations Functional Description Logic Block Diagram (CY7C1561V18) Logic Block Diagram (CY7C1576V18) CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev. *F Page 3 of 28 Logic Block Diagram (CY7C1563V18) Logic Block Diagram (CY7C1565V18) Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Pin Definitions CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 NC NC Pin Definitions CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example Truth Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Page TAP Controller State Diagram CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Boundary Scan Order Power Up Sequence in QDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) VDD/VDDQ DOFF Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Document Number: 001-05384 Rev. *F Page 24 of 28 Switching Waveforms NOPREAD QVLD Read/Write/Deselect Sequence Figure 5. Waveform for 2.5 Cycle Read Latency RPS Page Ordering Information Document Number: 001-05384 Rev. *F Page 27 of 28 Package Diagram [+] Feedback [+] Feedback Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195 51-85195-*A Document History Page