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Cypress CY7C1561V18, CY7C1563V18, CY7C1565V18, CY7C1576V18 NOPREAD, NOP WRITE READ WRITE 123 4 567 8

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CY7C1561V18, CY7C1576V18

CY7C1563V18, CY7C1565V18

Document Number: 001-05384 Rev. *F Page 24 of 28

Switching Waveforms

Read/Write/Deselect Sequence [31, 32, 33]

Figure 5. Waveform for 2.5 Cycle Read Latency

tKH tKL tCYC tKHKH

ttSA HA

SC HC

tHD

tSC tHC

A0 A1 A2 A3

tSD

D11

D10 D12 D13 D30 D31 D32 D33

D

A

WPS

RPS

NOPREADNOP WRITE READ WRITE123 4 5678

CQ

Q

tCQOH

CCQO

CLZ

tCO

tDOH tCQDOH

CQD

ttCHZ

tCQOH CCQO

tQVLD

QVLD

DON’T CARE UNDEFINED

(Read Latency = 2.5 Cycles)

Q00 Q01 Q20Q02 Q21

Q03 Q22 Q23

tCQH t

CQHCQH

Notes

31.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

32.Outputs are disabled (High-Z) one clock cycle after a NOP.

33.In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note

applies to the whole diagram.

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Contents

Main 72-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Features Configurations Functional Description Logic Block Diagram (CY7C1561V18) Logic Block Diagram (CY7C1576V18) CY7C1563V18, CY7C1565V18 Document Number: 001-05384 Rev. *F Page 3 of 28 Logic Block Diagram (CY7C1563V18) Logic Block Diagram (CY7C1565V18) Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Pin Definitions CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 NC NC Pin Definitions CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example Truth Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Page TAP Controller State Diagram CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Boundary Scan Order Power Up Sequence in QDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) VDD/VDDQ DOFF Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Document Number: 001-05384 Rev. *F Page 24 of 28 Switching Waveforms NOPREAD QVLD Read/Write/Deselect Sequence Figure 5. Waveform for 2.5 Cycle Read Latency RPS Page Ordering Information Document Number: 001-05384 Rev. *F Page 27 of 28 Package Diagram [+] Feedback [+] Feedback Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195 51-85195-*A Document History Page