Digi NS9750 manuals
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5 Contents21 Using This Guide RAbout this guide Who should read this guide 22 Whats in this guideThis table shows where you can find specific information in the printed guides. 23 Conventions used in this guideRelated documentation Documentation updates 24 Customer support26 NS9750 FeaturesSystem-level interfaces 32 NS975034 System bootReset 37 System clock39 USB clockTank Circuit X2_USB_OSC Figure 5: USB clock NS9750NOTE: ** = OPTIONAL Crystal circuit X1_USB_OSC 42 Pinout and signal descriptionsEach pinout table applies to a specific interface, and contains the following information: System Memory interfaceMore detailed signal descriptions are provided for selected modules. 46 System Memory interface signals49 Ethernet interfaceTable 5: Ethernet interface pinoutCKE NC7SB3157 reset_done clk_en[n] SDRAMNS9750 50 Clock generation/system pins52 bist_en_n, pll_test_n, and scan_en_nTable7 is a truth/termination table for bist_en_n, pll_test_n, and scan_en_n. All output drivers for PCI meet the standard PCI driver specification. PCI interface 57 P C IFigure 8: NS9750 unused PCI termination 58 GPIO MUX66 LCD module signalsThe CLD[23:0] signal has eight modes of operation: See the discussion of LCD panel signal multiplexing details for information about the Table 11: LCD module signal descriptions 67 I2C interfaceUSB interfaceTable 14: JTAG interface/boundary scan pinout attached. See Figure 9, "JTAG interface," on page44. through a 15K ohm resistor. JTAG interface for ARM core/boundary scanTable 12: I2C interface pinout Table 13: USB interface pinoutPinout and signal descriptions 68 Figure 9: JTAG interface44 Bits Signal name U/D OD (mA) I/O Description Table 14: JTAG interface/boundary scan pinoutJTAG 20 PIN HEADER.. NS9750 69 Reserved70 Power groundTable 16: Power ground pins 72 About the processorFigure 10 shows the main blocks in the ARM926EJ-S processor.Figure 10: ARM926EJ-S processor block diagram 73 Instruction setsThe processor executes three instruction sets:32-bit ARM instruction set 16-bit Thumb instruction set 8-bit Java instruction set 75 System control processor (CP15) registers101 Jazelle (Java)102 DSPMemory Management Unit (MMU) 129 Caches and write buffer135 Noncachable instruction fetches137 Instruction Memory BarrierIMB operation 138 Sample IMB sequences140 117 Note: Synchronous static memory devices (synchronous burst mode) are not supported. 141 System overviewThe largest amount of memory allowed for a single chip select is 256 MB. Figure 40 shows the NS9750 memory controller in a sample system.Figure 40: NS9750 sample system 142 Low-power operationMemory map 145 Static memory controllerTable 48: Static memory controller configurations Notes: memory performance. If the transaction order is important, the buffers must be disabled. 146 Write protecti onExtended wait transfers 147 Memory mapped peripheralsStatic memory initialization 173 Byte lane control174 Address connectivity178 Byte lane control and databus steeringTable 79: Little endian read, 8-bit external bus 179 Table 80: Little endian read, 16-bit external busTable 81: Little endian read, 32-bit external bus 180 Table 82: Little endian write, 8-bit external busTable 81: Little endian read, 32-bit external bus 181 Table 83: Little endian write, 16-bit external busTable 84: Little endian write, 32-bit external bus 182 Table 85: Big endian read, 8-bit external busTable 84: Little endian write, 32-bit external bus 183 Table 86: Big endian read, 16-bit external busTable 87: Big endian read, 32-bit external bus 184 Table 88: Big endian write, 8-bit external busTable 87: Big endian read, 32-bit external bus 185 Table 89: Big endian write, 16-bit external busTable 90: Big endian write, 32-bit external bus 186 Dynamic memory controllerWrite protecti on Access sequencing and memory width 187 Address mapping188 189 Table 91: Address mapping for 16M SDRAM (1Mx16, RBC)Table 92: Address mapping for 16M SDRAM (2Mx8, RBC) 190 Table 92: Address mapping for 16M SDRAM (2Mx8, RBC)Table 93: Address mapping for 64M SDRAM (2Mx32, RBC) 191 Table 94: Address mapping for 64M SDRAM (4Mx16, RBC)192 Table 96: Address mapping for 128M SDRAM (4Mx32, RBC)Table 95: Address mapping for 64M SDRAM (8Mx8, RBC) 193 Table 96: Address mapping for 128M SDRAM (4Mx32, RBC)Table 97: Address mapping for 128 SDRAM (8Mx16, RBC) 194 Table 97: Address mapping for 128 SDRAM (8Mx16, RBC)Table 98: Address mapping for 128 SDRAM (16Mx8, RBC) 195 Table 98: Address mapping for 128 SDRAM (16Mx8, RBC)Table 99: Address mapping for 256 SDRAM (8Mx32, RBC) 196 Table100 shows the outputs from the memory controller and the corresponding Table101 shows the outputs from the memory controller and the corresponding Table 101: Address mapping for 256M SDRAM (32Mx8, RBC) Table 100: Address mapping for 256M SDRAM (16Mx16, RBC) 197 Table102 shows the outputs from the memory controller and the corresponding Table 101: Address mapping for 256M SDRAM (32Mx8, RBC) Table 102: Address mapping for 512M SDRAM (32Mx16, RBC) 198 Table103 shows the outputs from the memory controller and the corresponding Table 102: Address mapping for 512M SDRAM (32Mx16, RBC) Table 103: Address mapping for 512M SDRAM (64Mx8, RBC) 199 Table 103: Address mapping for 512M SDRAM (64Mx8, RBC)Table 104: Address mapping for 16M SDRAM (1Mx16, BRC) 200 Table 106: Address mapping for 64M SDRAM (2Mx32, BRC)Table 105: Address mapping for 16M SDRAM (2Mx8, BRC) 201 Table107 shows the outputs from the memory controller and the corresponding Table 106: Address mapping for 64M SDRAM (2Mx32, BRC) Table 107: Address mapping for 64M SDRAM (4Mx16, BRC) 202 Table 107: Address mapping for 64M SDRAM (4Mx16, BRC)Table 108: Address mapping for 64M SDRAM (8Mx8, BRC) 203 Table 108: Address mapping for 64M SDRAM (8Mx8, BRC)Table 109: Address mapping for 128M SDRAM (4Mx32, BRC) 204 Table 111: Address mapping for 128M SDRAM (16Mx8, BRC)Table 110: Address mapping for 128M SDRAM (8Mx16, BRC) 205 Table 111: Address mapping for 128M SDRAM (16Mx8, BRC)Table 112: Address mapping for 256M SDRAM (8Mx32, BRC) 206 Table113 shows the outputs from the memory controller and the corresponding Table 112: Address mapping for 256M SDRAM (8Mx32, BRC) Table 113: Address mapping for 256M SDRAM (16Mx16, BRC) 207 Table114 shows the outputs from the memory controller and the corresponding Table 113: Address mapping for 256M SDRAM (16Mx16, BRC) Table 114: Address mapping for 256M SDRAM (32Mx8, BRC) 208 Table115 shows the outputs from the memory controller and the corresponding Table116 shows the outputs from the memory controller and the corresponding Table 116: Address mapping for 512M SDRAM (64x8, BRC) Table 115: Address mapping for 512M SDRAM (32Mx16, BRC) 209 Table 116: Address mapping for 512M SDRAM (64x8, BRC)Table 117: Address mapping for 16M SDRAM (1Mx16, RBC) 210 Table 117: Address mapping for 16M SDRAM (1Mx16, RBC)Table 118: Address mapping for 16M SDRAM (2Mx8, RBC) 211 Table119 shows the outputs from the memory controller and the corresponding Table 118: Address mapping for 16M SDRAM (2Mx8, RBC) Table 119: Address mapping for 64M SDRAM (4Mx16, RBC) 212 Table 121: Address mapping for 128M SDRAM (8Mx16, RBC)Table 120: Address mapping for 64M SDRAM (8Mx8, RBC) 213 Table 121: Address mapping for 128M SDRAM (8Mx16, RBC)Table 122: Address mapping for 128M SDRAM (16Mx8, RBC) 214 Table123 shows the outputs from the memory controller and the corresponding Table 122: Address mapping for 128M SDRAM (16Mx8, RBC) Table 123: Address mapping for 256M SDRAM (16Mx16, RBC) 215 Table124 shows the outputs from the memory controller and the corresponding Table 123: Address mapping for 256M SDRAM (16Mx16, RBC) Table 124: Address mapping for 256M SDRAM (32Mx8, RBC) 216 Table125 shows the outputs from the memory controller and the corresponding Table 125: Address mapping for 512M SDRAM (32Mx16, RBC) 218 Table 127: Address mapping for 16M SDRAM (1Mx16, BRC)Table 128: Address mapping for 16M SDRAM (2Mx8, BRC) 219 Table129 shows the outputs from the memory controller and the corresponding Table 128: Address mapping for 16M SDRAM (2Mx8, BRC) Table 129: Address mapping for 64M SDRAM (4Mx16, BRC) 220 Table 129: Address mapping for 64M SDRAM (4Mx16, BRC)Table 130: Address mapping for 64M SDRAM (8Mx8, BRC) 221 Table 132: Address mapping for 128M SDRAM (16Mx8, BRC)Table 131: Address mapping for 128M SDRAM (8Mx16, BRC) 222 Table 132: Address mapping for 128M SDRAM (16Mx8, BRC)Table 133: Address mapping for 256M SDRAM (16Mx16, BRC) 223 Table 133: Address mapping for 256M SDRAM (16Mx16, BRC)Table 134: Address mapping for 256M SDRAM (32Mx8, BRC) 224 Table135 shows the outputs from the memory controller and the corresponding Table 134: Address mapping for 256M SDRAM (32Mx8, BRC) Table 135: Address mapping for 512M SDRAM (32Mx16, BRC) 225 Table136 shows the outputs from the memory controller and the corresponding Table 136: Address mapping for 512M SDRAM (64Mx8, BRC) 226 Registers278 System Control Module featuresBus interconnection System bus arbiter 285 Address decoding287 Programmable timersSoftware watchdog timer General purpose timers/counters 291 Interrupt controller295 System attributesPLL configurationSystem attributes Figure 62 shows how the PLL clock is used to provide the NS9750 system clocks.Figure 62: NS9750 system clock generation (PLL) 296 Bootstrap initialization300 System configuration registers306 AHB Arbiter Gen Configuration registerAddress: A090 0000 Table 171: AHB Arbiter Gen Configuration register 307 BRC0, BRC1, BRC2, and BRC3 registers308 Timer 015 Reload Count registersThe Timer Reload registers hold the up/down reload value.Table 173: BRC0, BRC1, BRC2, BRC3 register Table 174: Timer Reload Count register 309 Timer 015 Read registerThe Timer Read registers read the current state of each Timer register. Interrupt Vector Address Register Level 031 310 Int (Interrupt) Config (Configuration) registers (031)312 ISRADDR register313 Interrupt Status Active Address: A090 0168 The Interrupt Status Active register shows the current interrupt request.Table 180: Interrupt Status Active register 314 Interrupt Status RawAddress: A090 016C The Interrupt Status Raw register shows all current interrupt requests.Table 181: Interrupt Status Raw register 315 Timer Interrupt Status registerAddress: A090 0170 The Timer Interrupt Status register shows all current timer interrupt requests. Software Watchdog Configuration registerAddress: A090 0174 The Software Watchdog Configuration register configures the software watchdog timer operation. 317 Software Watchdog Timer registerAddress: A090 0178 The Software Watchdog Timer register services the watchdog timer. Clock Configuration registerAddress: A090 017C The Clock Configuration register enables and disables clocks to each module on the AHB bus. 319 Reset and Sleep Control register320 Miscellaneous System Configuration and Status registerTable 186: Reset and Sleep Control register Address: A090 0184 323 PLL Configuration registerAddress: A090 0188 The PLL Configuration register configures the PLL. 325 Active Interrupt Level Status registerAddress: A090 018C The Active Interrupt Level Status register shows the current active interrupt level. Timer 015 Control registers 327 System Memory Chip Select 0 Dynamic Memory Base and Mask registersTable 190: Timer Control register Address: A090 01D0 / 01D4 328 System Memory Chip Select 1 Dynamic Memory Base and Mask registersAddress: A090 01D8 / 01DC Table 191: System Memory Chip Select 0 Dynamic Memory Base & Mask registers 329 System Memory Chip Select 2 Dynamic Memory Base and Mask registersAddress: A090 01E0 / 01E4 These control registers set the base and mask for system memory chip select 6, with Table 192: System Memory Chip Select 1 Dynamic Memory Base & Mask registers 330 System Memory Chip Select 3 Dynamic Memory Base and Mask registersAddress: A090 01E8 / 01EC Table 193: System Memory Chip Select 2 Dynamic Memory Base & Mask registers 331 System Memory Chip Select 0 Static Memory Base and Mask registersAddress: A090 01F0 / 01F4 These control registers set the base and mask for system memory chip select 0, with Table 194: System Memory Chip Select 3 Dynamic Memory Base & Mask registers 332 System Memory Chip Select 1 Static Memory Base and Mask registersAddress: A09001F8 / 01FC Table 195: System Memory Chip Select 0 Static Memory Base & Mask registers 333 System Memory Chip Select 2 Static Memory Base and Mask registersAddress: A090 0200 / 0204 These control registers set the base and mask for system memory chip select 2, with Table 196: System Memory Chip Select 1 Memory Base and Mask registers 334 System Memory Chip Select 3 Static Memory Base and Mask registersAddress: A090 0208 / 020C These control registers set the base and mask for system memory chip select 3, with Table 197: System Memory Chip Select 2 Static Memory Base & Mask registers 335 Gen ID registerAddress: A090 0210 This register is read-only, and indicates the state of GPIO pins at powerup. 337 External Interrupt 03 Control registerAddress: A090 0214 / 0218 / 021C / 0220 Table 200: External Interrupt 03 Control register 341 Ethernet MAC347 Ethernet front-end module358 External CAM filtering361 Ethernet Control and Status registers421 Sample hash table code428 About the PCI-to-AHB Bridge442 PCI bus arbiter480 PCI system configurationsNS9750Figure 72: System connections to NS9750 Internal arbiter and central resources1These pins are not connected because internal resistors tie these pins to the appropriate state. 481 NS9750External PCI Arbiter 485 CardBus Support492 BBus bridge functions493 Bridge control logic496 BBus control logic498 Two-channel AHB DMA controller (AHB bus)507 Interrupt aggregationBandwidth requirements 508 SPI-EEPROM boot logic514 BBus Bridge Control and Status registers526 About the BBus DMA controllers527 DMA context memory528 DMA buffer descriptor533 DMA channel assignments534 DMA Control and Status registers546 BBus Utility Control and Status registers 567 I2C Master/Slave InterfaceT 871 Index
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