Digi NS9750 X

Overview

674

NS9750 Hardware Reference

Figure 99: ECP mode forward transfer cycles

XHost processing sequence example:

1The host puts the data on the data lines and indicates a data cycle by setting

HostAck high.

2The host asserts HostClk low to indicate valid data.

3The peripheral acknowledges the host by setting PeriphAck to high.

4The host sets HostClk to high. This edge should be used to latch the data into the

peripheral.

5The peripheral sets PeriphAck low, indicating that it’s ready for the next data byte.

6The host sets HostAck to low to start the command transfer.

Note:

A forward transfer does not have to be a data transfer followed by a

command transfer. When HostClk is low, th e tran sfe r will be data or

command depending on whether HostAck is high or low.

Reverse transfer cycles

With the ECP protocol, changes in the data direction must be negotiated.

The host must request a reverse channel transfer by asserting the ReverseRequest signal.

The host waits for the peripheral to acknowledge the request by asserting the

AckReverse signal. Only then can a reverse channel data transfer take place.

Figure 100 shows a reverse channel data cycle followed by a command cycle. In this

case, PeriphClk is the data strobe and HostAck is the acknowledge signal.

Contents

Main Page Page Page Contents Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Using This Guide R About this guide Who should read this guide Whats in this guide This table shows where you can find specific information in the printed guides. Conventions used in this guide Related documentation Documentation updates Customer support Page NS9750 Features Page Page Page Page Page System-level interfaces NS9750 Page System boot Reset RESET_DONE as an input RESET_DONE as an output Page System clock NS9750 About NS9750 USB clock Tank Circuit X2_USB_OSC Figure 5: USB clock NS9750 Page Page Pinout and signal descriptions Each pinout table applies to a specific interface, and contains the following information: System Memory interface More detailed signal descriptions are provided for selected modules. Page Page Page System Memory interface signals Table 4: System Memory interface signal descriptions Pinout and signal descriptions Figure 6 shows NS9750 SDRAM clock termination. Figure 6: SDRAM clock termination Figure 7: NS9750 clock enable configuration Ethernet interface Table 5: Ethernet interface pinout CKE NC7SB3157 reset_done Clock generation/system pins Table 5: Ethernet interface pinout Table 6: Clock generation and system pin pinout bist_en_n, pll_test_n, and scan_en_n Table7 is a truth/termination table for bist_en_n, pll_test_n, and scan_en_n. All output drivers for PCI meet the standard PCI driver specification. PCI interface The PCI interface can be set to PCI host or PCI device (slave) using the pci_central_rsc_n pin. Page Page Page Table 9: CardBus IO multiplexed signals NS9750 Pinout P C I Figure 8: NS9750 unused PCI termination GPIO MUX Page Page Page Page Page Page Example: Implementing gpio[16] and gpio[17] USB Pow er Controller NS97xx LCD module signals The CLD[23:0] signal has eight modes of operation: See the discussion of LCD panel signal multiplexing details for information about the Table 11: LCD module signal descriptions I2C interface USB interface Table 14: JTAG interface/boundary scan pinout attached. See Figure 9, "JTAG interface," on page44. through a 15K ohm resistor. Figure 9: JTAG interface 44 Bits Signal name U/D OD (mA) I/O Description Table 14: JTAG interface/boundary scan pinout JTAG 20 PIN HEADER.. Reserved Table 15: Reserved pins Power ground Table 16: Power ground pins Page About the processor Figure 10 shows the main blocks in the ARM926EJ-S processor. Figure 10: ARM926EJ-S processor block diagram Instruction sets The processor executes three instruction sets: 32-bit ARM instruction set 16-bit Thumb instruction set 8-bit Java instruction set Page System control processor (CP15) registers ARM926EJ-S system addresses Accessing CP15 registers Terms and abbreviations Register summary Table 18: CP15 register summary R0: ID code and cache type status registers Page Dsize and Isize fields R1: Control register Table 22: R1: Control register bit definition The M, C, I, and RR bits directly affect ICache and DCache behavior, as shown: Table 22: R1: Control register bit definition Table 23: Effects of Control register on caches R2: Translation Table Base register R3: Domain Access Control register R4 register R5: Fault Status registers Figure 16: Fault Status registers format Table 24: Fault Status register bit description Table 25: Fault Status register status field encoding R6: Fault Address register R7: Cache Operations register Table 26: Cache Operations register function descriptions Table 27: R7: Cache operations Table 26: Cache Operations register function descriptions Page R8:TLB Operations register R9: Cache Lockdown register Page Page Page R10: TLB Lockdown register R11 and R12 registers R13: Process ID register Page R14 register R15: Test and debug register Jazelle (Java) DSP Memory Management Unit (MMU) MMU Features Page Page Address translation Page Figure 25 shows the table walk process. Figure 25: Translating page tables Page describes into 1 KB blocks. Figure 27: First-level descriptor Table 32: Priority encoding of fault status Table32 shows first-level descriptor bit assignments. Figure 28: Section descriptor Table 34: Section descriptor bits Table 33: Interpreting first-level descriptor bits [1:0] Table 32: Priority encoding of fault status Page Page Page Page Page Figure 33: Large page translation from a coarse page table Figure 34: Small page translation from a coarse page table Figure 35: Tiny page translation from a fine page table MMU faults and CPU aborts Page Page Domain access control Fault checking sequence Table 42: Interpreting access permission (AP) bits Figure 36: Sequence for checking faults The conditions that generate each of the faults are discussed in the following sections. Page External aborts Enabling the MMU Disabling the MMU TLB structure Caches and write buffer Cache features Write buffer Enabling the caches Table 45: R1: Control register I and M bit settings for DCache Table 46: Page table C and B bit settings for DCache Cache MVA and Set/Way formats Figure 37: Generic virtually indexed, virtually addressed cache Page Noncachable instruction fetches Self-modifying code AHB behavior Instruction Memory Barrier IMB operation Sample IMB sequences Page 117 Memory Controller Note: Synchronous static memory devices (synchronous burst mode) are not supported. System overview The largest amount of memory allowed for a single chip select is 256 MB. Figure 40 shows the NS9750 memory controller in a sample system. Figure 40: NS9750 sample system Low-power operation Memory map Page Static memory controller Table 48: Static memory controller configurations Notes: memory performance. If the transaction order is important, the buffers must be disabled. Write protecti on Extended wait transfers Memory mapped peripherals Static memory initialization Page Page Figure 42: External memory 2 wait state read timing diagram Table 50: External memory 0 wait state read Table 51: Static memory timing parameters Page Page Table55 provides the timing parameters. Table 56 describes the transactions for Figure 44. Figure 44: External memory 2 0 wait state read timing diagram Table 55: Static memory timing parameters Table 56: External memory 2 0wait state reads Page Table 57: SRAM timing parameters Table 58: External memory zero wait fixed length burst read Figure 46: External memory 2 wait states fixed length burst read timing diagram Table 59: SRAM timing diagrams Table 60: External memory 2 wait states fixed length burst read Page Figure 47: External memory page mode read transfer timing diagram Table 61: Static memory timing parameters Table 62: External memory page mode read describes the transactions for Figure 48. Table 63: Static memory timing parameters Figure 48: External memory 32-bit burst read from 8-bit memory timing diagram Table 62: External memory page mode read Page Page Table 65: Static memory timing parameters Table 66: External memory 0 wait state write Figure 50: External memory 2 wait state write timing diagram Table 67: Static memory timing parameters Table 68: External memory 2 wait state write Figure 51: External memory 2 write enable delay write timing diagram Table 69: Static memory timing parameters Table 68: External memory 2 wait state write Page Figure 52: External memory 2 0 wait writes timing diagram Table 71: Static memory timing parameters Table 72: External memory 2 0 wait writes Page Figure 53: Read followed by write (both 0 wait) with no turnaround Table 73: Static memory timing parameters Table 74: Read followed by write (both 0 wait) with no turnaround Page Table75 provides the timing parameters. Table 76 describes the transactions for Figure 54. Figure 54: Write followed by a read (both 0 wait) with no turnaround Table 75: Static memory timing parameters Table 76: Write followed by read (both 0 wait) with no turnaround Page Table77 provides the timing parameters. Table 78 describes the transactions for Figure 55. Figure 55: Read followed by a write (all 0 wait state) with two turnaround cycles Table 78: Read followed by a write (all 0 wait state) with two turnaround cycles Table 77: Static memory timing parameters Byte lane control Static memory controller Address connectivity Page Static memory controller Figure 58: Memory banks constructed from 32-bit memory Figure 59 shows connections for a typical memory system with different data width memory devices. Memory Controller Figure 59: Typical memory connection diagram (1) Byte lane control and databus steering Table 79: Little endian read, 8-bit external bus Table 80: Little endian read, 16-bit external bus Table 81: Little endian read, 32-bit external bus Table 82: Little endian write, 8-bit external bus Table 81: Little endian read, 32-bit external bus Table 83: Little endian write, 16-bit external bus Table 84: Little endian write, 32-bit external bus Table 85: Big endian read, 8-bit external bus Table 84: Little endian write, 32-bit external bus Table 86: Big endian read, 16-bit external bus Table 87: Big endian read, 32-bit external bus Table 88: Big endian write, 8-bit external bus Table 87: Big endian read, 32-bit external bus Table 89: Big endian write, 16-bit external bus Table 90: Big endian write, 32-bit external bus Dynamic memory controller Write protecti on Access sequencing and memory width Address mapping Page Table 91: Address mapping for 16M SDRAM (1Mx16, RBC) Table 92: Address mapping for 16M SDRAM (2Mx8, RBC) Table 92: Address mapping for 16M SDRAM (2Mx8, RBC) Table 93: Address mapping for 64M SDRAM (2Mx32, RBC) Table 94: Address mapping for 64M SDRAM (4Mx16, RBC) Table 96: Address mapping for 128M SDRAM (4Mx32, RBC) Table 95: Address mapping for 64M SDRAM (8Mx8, RBC) Table 96: Address mapping for 128M SDRAM (4Mx32, RBC) Table 97: Address mapping for 128 SDRAM (8Mx16, RBC) Table 97: Address mapping for 128 SDRAM (8Mx16, RBC) Table 98: Address mapping for 128 SDRAM (16Mx8, RBC) Table 98: Address mapping for 128 SDRAM (16Mx8, RBC) Table 99: Address mapping for 256 SDRAM (8Mx32, RBC) Table100 shows the outputs from the memory controller and the corresponding Table101 shows the outputs from the memory controller and the corresponding Table 101: Address mapping for 256M SDRAM (32Mx8, RBC) Table 100: Address mapping for 256M SDRAM (16Mx16, RBC) Table102 shows the outputs from the memory controller and the corresponding Table 101: Address mapping for 256M SDRAM (32Mx8, RBC) Table 102: Address mapping for 512M SDRAM (32Mx16, RBC) Table103 shows the outputs from the memory controller and the corresponding Table 102: Address mapping for 512M SDRAM (32Mx16, RBC) Table 103: Address mapping for 512M SDRAM (64Mx8, RBC) Table 103: Address mapping for 512M SDRAM (64Mx8, RBC) Table 104: Address mapping for 16M SDRAM (1Mx16, BRC) Table 106: Address mapping for 64M SDRAM (2Mx32, BRC) Table 105: Address mapping for 16M SDRAM (2Mx8, BRC) Table107 shows the outputs from the memory controller and the corresponding Table 106: Address mapping for 64M SDRAM (2Mx32, BRC) Table 107: Address mapping for 64M SDRAM (4Mx16, BRC) Table 107: Address mapping for 64M SDRAM (4Mx16, BRC) Table 108: Address mapping for 64M SDRAM (8Mx8, BRC) Table 108: Address mapping for 64M SDRAM (8Mx8, BRC) Table 109: Address mapping for 128M SDRAM (4Mx32, BRC) Table 111: Address mapping for 128M SDRAM (16Mx8, BRC) Table 110: Address mapping for 128M SDRAM (8Mx16, BRC) Table 111: Address mapping for 128M SDRAM (16Mx8, BRC) Table 112: Address mapping for 256M SDRAM (8Mx32, BRC) Table113 shows the outputs from the memory controller and the corresponding Table 112: Address mapping for 256M SDRAM (8Mx32, BRC) Table 113: Address mapping for 256M SDRAM (16Mx16, BRC) Table114 shows the outputs from the memory controller and the corresponding Table 113: Address mapping for 256M SDRAM (16Mx16, BRC) Table 114: Address mapping for 256M SDRAM (32Mx8, BRC) Table115 shows the outputs from the memory controller and the corresponding Table116 shows the outputs from the memory controller and the corresponding Table 116: Address mapping for 512M SDRAM (64x8, BRC) Table 115: Address mapping for 512M SDRAM (32Mx16, BRC) Table 116: Address mapping for 512M SDRAM (64x8, BRC) Table 117: Address mapping for 16M SDRAM (1Mx16, RBC) Table 117: Address mapping for 16M SDRAM (1Mx16, RBC) Table 118: Address mapping for 16M SDRAM (2Mx8, RBC) Table119 shows the outputs from the memory controller and the corresponding Table 118: Address mapping for 16M SDRAM (2Mx8, RBC) Table 119: Address mapping for 64M SDRAM (4Mx16, RBC) Table 121: Address mapping for 128M SDRAM (8Mx16, RBC) Table 120: Address mapping for 64M SDRAM (8Mx8, RBC) Table 121: Address mapping for 128M SDRAM (8Mx16, RBC) Table 122: Address mapping for 128M SDRAM (16Mx8, RBC) Table123 shows the outputs from the memory controller and the corresponding Table 122: Address mapping for 128M SDRAM (16Mx8, RBC) Table 123: Address mapping for 256M SDRAM (16Mx16, RBC) Table124 shows the outputs from the memory controller and the corresponding Table 123: Address mapping for 256M SDRAM (16Mx16, RBC) Table 124: Address mapping for 256M SDRAM (32Mx8, RBC) Table125 shows the outputs from the memory controller and the corresponding Table 125: Address mapping for 512M SDRAM (32Mx16, RBC) Page Table 127: Address mapping for 16M SDRAM (1Mx16, BRC) Table 128: Address mapping for 16M SDRAM (2Mx8, BRC) Table129 shows the outputs from the memory controller and the corresponding Table 128: Address mapping for 16M SDRAM (2Mx8, BRC) Table 129: Address mapping for 64M SDRAM (4Mx16, BRC) Table 129: Address mapping for 64M SDRAM (4Mx16, BRC) Table 130: Address mapping for 64M SDRAM (8Mx8, BRC) Table 132: Address mapping for 128M SDRAM (16Mx8, BRC) Table 131: Address mapping for 128M SDRAM (8Mx16, BRC) Table 132: Address mapping for 128M SDRAM (16Mx8, BRC) Table 133: Address mapping for 256M SDRAM (16Mx16, BRC) Table 133: Address mapping for 256M SDRAM (16Mx16, BRC) Table 134: Address mapping for 256M SDRAM (32Mx8, BRC) Table135 shows the outputs from the memory controller and the corresponding Table 134: Address mapping for 256M SDRAM (32Mx8, BRC) Table 135: Address mapping for 512M SDRAM (32Mx16, BRC) Table136 shows the outputs from the memory controller and the corresponding Table 136: Address mapping for 512M SDRAM (64Mx8, BRC) Registers Register map Table 137: Memory Controller register map Reset values Table 137: Memory Controller register map Control registe r Table 138: Control register Status r e g i s t e r Address: A070 0004 The Status register provides memory controller status information. Address: A070 0008 Configuration register Table 139: Status register Dynamic Memory Control register Address: A070 0020 Table 140: Configuration register Table 141: Dynamic Memory Control register Dynamic Memory Refresh Timer register Page Dynamic Memory Read Configuration register Dynamic Memory Precharge Command Period register Dynamic Memory Active to Precharge Command Period register Dynamic Memory Self-refresh Exit Time register Dynamic Memory Last Data Out to Active Time register Dynamic Memory Data-in to Active Command Time register Dynamic Memory Write Recovery Time register Dynamic Memory Active to Active Command Period register Dynamic Memory Auto Refresh Period register Dynamic Memory Exit Self-refresh register Dynamic Memory Active Bank A to Active Bank B Time register Dynamic Memory Load Mode register to Active Command Time register Static Memory Extended Wait register Dynamic Memory Configuration 03 registers Table 156: Dynamic Memory Configuration 03 registers Page Page Dynamic Memory RAS and CAS Delay 03 registers Static Memory Configuration 03 registers Page Page Synchronous burst mode memory devices are not supported. Static Memory Write Enable Delay 03 registers Static Memory Output Enable Delay 03 registers Static Memory Read Delay 03 registers Static Memory Page Mode Read Delay 03 registers Static Memory Write Delay 03 registers Static Memory Turn Round Delay 03 registers Page Page Page Page Page Page Page Page Page Page Page Page Page Page System Control Module features Bus interconnection System bus arbiter Page Page Page Arbiter configuration examples Page Page Address decoding Table 166: System address map Table 167: Hmaster encoding Programmable timers Software watchdog timer General purpose timers/counters Page Page Interrupt controller Page The NS9750 interrupt sources are assigned as shown: Vectored interrupt controller (VIC) flow System attributes PLL configuration System attributes Figure 62 shows how the PLL clock is used to provide the NS9750 system clocks. Figure 62: NS9750 system clock generation (PLL) Bootstrap initialization Table 168: Configuration pins Bootstrap initialization Table 169: PLL ND[4:0] multiplier values Table 168: Configuration pins Bootstrap initialization Table 169: PLL ND[4:0] multiplier values System configuration registers Page Page Page Page Page AHB Arbiter Gen Configuration register Address: A090 0000 Table 171: AHB Arbiter Gen Configuration register BRC0, BRC1, BRC2, and BRC3 registers Timer 015 Reload Count registers The Timer Reload registers hold the up/down reload value. Table 173: BRC0, BRC1, BRC2, BRC3 register Table 174: Timer Reload Count register Timer 015 Read register The Timer Read registers read the current state of each Timer register. Interrupt Vector Address Register Level 031 Int (Interrupt) Config (Configuration) registers (031) Table 178: Int Config register ISRADDR register Interrupt Status Active Address: A090 0168 The Interrupt Status Active register shows the current interrupt request. Table 180: Interrupt Status Active register Interrupt Status Raw Address: A090 016C The Interrupt Status Raw register shows all current interrupt requests. Table 181: Interrupt Status Raw register Timer Interrupt Status register Address: A090 0170 The Timer Interrupt Status register shows all current timer interrupt requests. Software Watchdog Configuration register Address: A090 0174 Table 183: Software Watchdog Configuration register Software Watchdog Timer register Address: A090 0178 The Software Watchdog Timer register services the watchdog timer. Clock Configuration register Address: A090 017C Table 185: Clock Configuration register Reset and Sleep Control register Miscellaneous System Configuration and Status register Table 186: Reset and Sleep Control register Address: A090 0184 Page Page PLL Configuration register Address: A090 0188 The PLL Configuration register configures the PLL. Table 188: PLL Configuration register Active Interrupt Level Status register Address: A090 018C The Active Interrupt Level Status register shows the current active interrupt level. Timer 015 Control registers Table 189: Active Interrupt Level Status register Table 190: Timer Control register System Memory Chip Select 0 Dynamic Memory Base and Mask registers Table 190: Timer Control register Address: A090 01D0 / 01D4 System Memory Chip Select 1 Dynamic Memory Base and Mask registers Address: A090 01D8 / 01DC Table 191: System Memory Chip Select 0 Dynamic Memory Base & Mask registers System Memory Chip Select 2 Dynamic Memory Base and Mask registers Address: A090 01E0 / 01E4 These control registers set the base and mask for system memory chip select 6, with Table 192: System Memory Chip Select 1 Dynamic Memory Base & Mask registers System Memory Chip Select 3 Dynamic Memory Base and Mask registers Address: A090 01E8 / 01EC Table 193: System Memory Chip Select 2 Dynamic Memory Base & Mask registers System Memory Chip Select 0 Static Memory Base and Mask registers Address: A090 01F0 / 01F4 These control registers set the base and mask for system memory chip select 0, with Table 194: System Memory Chip Select 3 Dynamic Memory Base & Mask registers System Memory Chip Select 1 Static Memory Base and Mask registers Address: A09001F8 / 01FC Table 195: System Memory Chip Select 0 Static Memory Base & Mask registers System Memory Chip Select 2 Static Memory Base and Mask registers Address: A090 0200 / 0204 These control registers set the base and mask for system memory chip select 2, with Table 196: System Memory Chip Select 1 Memory Base and Mask registers System Memory Chip Select 3 Static Memory Base and Mask registers Address: A090 0208 / 020C These control registers set the base and mask for system memory chip select 3, with Table 197: System Memory Chip Select 2 Static Memory Base & Mask registers Gen ID register Address: A090 0210 This register is read-only, and indicates the state of GPIO pins at powerup. Table 198: System Memory Chip Select 3 Static Memory Base & Mask registers Table 199: General Purpose ID register External Interrupt 03 Control register Address: A090 0214 / 0218 / 021C / 0220 Table 200: External Interrupt 03 Control register Page Page Page Ethernet MAC Figure 64: Ethernet MAC block diagram Table 201: Ethernet MAC features Table 201: Ethernet MAC features Table 202: PHY interface mappings to external IO Station address logic (SAL) Statistics module Page Ethernet Communication Module Ethernet front-end module Figure 65 shows the Ethernet front-end module (EFE). Figure 65: Ethernet front-end module block diagram Receive packet processor Page used is read from system memory and stored in the registers internal to the RX_RD logic. Figure 66: Receive buffer descriptor format Transmit packet processor Figure 67: Transmit buffer descriptor format Page Page Ethernet Slave Interface Interrupts Table 203: Ethernet interrupt conditions Resets Table 204: Reset control Table 203: Ethernet interrupt conditions Table 204: Reset control External CAM filtering Page Page Ethernet Control and Status registers Table 205: Ethernet Control and Status register map Ethernet General Control Register #1 Address: A060 0000 Page Page Ethernet General Control Register #2 Address: A060 0004 Table 207: Ethernet General Control Register #2 Ethernet General Status register Ethernet Transmit Status register Page Table 209: Ethernet Transmit Status register Ethernet Receive Status register MAC Configuration Register #1 Table 210: Ethernet Receive Status register Address: A060 0400 Table 211: MAC Configuration Register #1 Page MAC Configuration Register #2 Address: A060 0404 Page PAD operation table for transmit frames Back-to-Back Inter-Packet-Gap register Address: A060 0408 Table 213: Back-to-Back Inter-Packet-Gap register Non Back-to-Back Inter-Packet-Gap register Address: A060 040C Address: A060 0410 Collision Window/Retry register Table 214: Non Back-to-Back Inter-Packet-Gap register Table 215: Collision Window/Retry register Maximum Frame register Address: A060 0414 Table 216: Maximum Frame register PHY Support register Address: A060 0418 Table 217: PHY Support register MII Management Configuration register Address: A060 0420 Table 218: MII Management Configuration register Clocks field settings MII Management Command register If both SCAN and READ are set, SCAN takes precedence. Address: A060 0424 Table 219: MII Management Command register MII Management Address register Address: A060 0428 Table 219: MII Management Command register Table 220: MII Management Address register MII Management Write Data register Address: A060 042C Table 220: MII Management Address register Table 221: MII Management Write Data register MII Management Read Data register Address: A060 0430 MII Management Indicators register Address: A060 0434 Table 222: MII Management Read Data register Station Address registers Address: A060 0440 / 0444 / 0448 Table 223: MII Management Indicators register Table 224: Station Address registers Station Address Filter register Register Hash Tables Page Statis t i c s r e g i s t ers Receive statistics counters Receive byte counter (A060 069C) Table 229: Receive statistics counters address map Page Page Page Table 230: Transmit statistics counters address map Page Page Page Page Carry Register 1 Table 232: Carry Register 1 Carry Register 2 Table 233: Carry Register 2 Table 232: Carry Register 1 Carry Register 1 Mask register Table 234: Carry Register 1 Mask register Table 233: Carry Register 2 Table 234: Carry Register 1 Mask register Carry Register 2 Mask register Table 235: Carry Register 2 Mask register RX_A Buffer Descriptor Pointer register Address: A060 0A00 RX_B Buffer Descriptor Pointer register Address: A060 0A04 Table 236: RX_A Buffer Descriptor Pointer register RX_C Buffer Descriptor Pointer register Address: A060 0A08 RX_D Buffer Descriptor Pointer register Address: A060 0A0C Table 238: RX_C Buffer Descriptor Pointer Ethernet Interrupt Status register Table 240: Ethernet Interrupt Status register Ethernet Interrupt Enable register Table 240: Ethernet Interrupt Status register Address: A060 0A14 Table 241: Ethernet Interrupt Enable register TX Buffer Descriptor Pointer register Address: A060 0A18 Transmit Recover Buffer Descriptor Pointer register Address: A060 0A1C Table 242: TX Buffer Descriptor Pointer register TX Error Buffer Descriptor Pointer register Address: A060 0A20 Table 243: Transmit Recover Buffer Descriptor Pointer register Table 244: TX Error Buffer Descriptor Pointer register RX_A Buffer Descriptor Pointer Offset register Address: A060 0A28 Table 244: TX Error Buffer Descriptor Pointer register RX_B Buffer Descriptor Pointer Offset register Address: A060 0A2C Table 245: RX_A Buffer Descriptor Pointer Offset register Table 246: RX_B Buffer Descriptor Pointer Offset register RX_C Buffer Descriptor Pointer Offset register Address: A060 0A30 RX_D Buffer Descriptor Pointer Offset register Address: A060 0A34 Table 247: RX_C Buffer Descriptor Pointer Offset register Transmit Buffer Descriptor Pointer Offset register Address: A060 0A38 Table 248: RX_D Buffer Descriptor Pointer Offset register Table 249: TX Buffer Descriptor Pointer Offset register RX Free Buffer register TX buffer descriptor RAM Sample hash table code Page Page Page Page Page Page About the PCI-to-AHB Bridge PCI-to-AHB Bridge PCI-to-AHB bridge functionality Figure 71: PCI-to-AHB bridge diagram Page Cross-bridge transaction error handling Table 251: PCI-to-AHB error handling AHB address decoding and translation PCI address decoding and mapping Interrupts Transaction ordering Endian configuration Configuration registers Table 253: CONFIG_ADDR register Bridge Configuration registers Page PCI Status register Table256 describes the PCI Status register fields. Table 256: PCI Status register Page Page PCI bus arbiter PCI arbiter functional description Slave interface PCI Arbiter Configuration registers Table 259: PCI arbiter register map Page PCI Arbiter Configuration register Address: A030 0000 Table 260: PCI Arbiter Configuration register PCI Arbiter Interrupt Status register Address: A030 0004 Table 261: PCI Arbiter Interrupt Status register Table 260: PCI Arbiter Configuration register PCI Arbiter Interrupt Enable register Address: A030 0008 Table 262: PCI Arbiter Interrupt Enable register Table 261: PCI Arbiter Interrupt Status register Page Table 263: PCI Miscellaneous Support register PCI Configuration 0 register Table 263: PCI Miscellaneous Support register Address: A030 0010 Page Page Page PCI Bridge Configuration register Address: A030 0020 Table 268: PCI Bridge Configuration register Table 267: PCI Configuration 3 register PCI Bridge AHB Error Address register Address: A030 0024 Table 269: PCI Bridge AHB Error Address register Address: A030 0028 PCI Bridge PCI Error Address register Page PCI Bridge Interrupt Enable register Address: A030 0030 The PCI Bridge Interrupt Enable register stores the enables for all interrupt sources. Table 271: PCI Bridge Interrupt Status register Table 272: PCI Bridge Interrupt Enable register PCI Bridge AHB to PCI Memory Address Translate 0 register Address: A030 0034 Table 273: PCI Bridge AHB-to-PCI Memory Address Translate 0 register PCI Bridge AHB to PCI Memory Address Translate 1 register Address: A030 0038 Table 274: PCI Bridge AHB-to-PCI Memory Address Translate 1 register Page PCI Bridge PCI to AHB Memory Address Translate 1 Address: A030 0044 Table 276: PCI Bridge PCI-to-AHB Memory Address Translate 0 register Table 277: PCI Bridge PCI-to-AHB Memory Address Translate 1 register PCI Bridge Address Translation Control register Address: A030 0048 Table 278: PCI Bridge Address Translation Control register Table 277: PCI Bridge PCI-to-AHB Memory Address Translate 1 register CardBus Miscellaneous Support register Address: A030 004C Table 278: PCI Bridge Address Translation Control register Page Page Page CardBus Socket Event register Address: A030 1000 CardBus Socket Mask register Table 280: CardBus Socket Event register Address: A030 1004 CardBus Socket Present State register Address: A030 1008 Table 281: CardBus Socket Mask register Page Table 282: Cardbus Socket Present State register Page Page Table 283: CardBus Socket Force Event register CardBus Socket Control register Address: A030 1010 The CardBus Socket Control register is used only for CardBus applications. Table 284: CardBus Socket Control register PCI system configurations 456 PCI system configurations NS9750 Figure 72: System connections to NS9750 Internal arbiter and central resources 1These pins are not connected because internal resistors tie these pins to the appropriate state. NS9750 External PCI Arbiter Device selection for configuration PCI interrupts PCI central resource functions Page Page CardBus Support CardBus Support Figure 74: CardBus system connections to NS9750 BOOT_STRAP[1] PCI_CENTRAL_RSC_n NS9750 IDSEL Confi g u r i n g NS9750 fo r CardB u s s u p p o r t CardBus adapter requirements CardBus interrupts Page Page BBus bridge functions Bridge control logic Page DMA accesses BBus control logic BBus bridge masters and slaves Cycles and BBus arbitration BBus peripheral address map (decoding) Two-channel AHB DMA controller (AHB bus) DMA buffer descriptor Page Descriptor list processing Table 289: BBus bridge DMA buffer descriptor definition Peripheral DMA read access Peripheral DMA write access Peripheral REQ signaling Design Limitations Calculating AHB DMA response latency Page Static RAM chip select configuration Table 290: Static RAM chip select configuration Interrupt aggregation Bandwidth requirements SPI-EEPROM boot logic Serial Channel B configuration Memory Controller configuration Table 293: ARM boot configuration SDRAM boot algorithm Page BBus Bridge Control and Status registers Buffer Descriptor Pointer register DMA Channel 1/2 Control register Page Page DMA Status and Interrupt Enable register Address: A040 0008 / 0028 Table 298: DMA Status and Interrupt Enable register bit definition DMA Peripheral Chip Select register Table 298: DMA Status and Interrupt Enable register bit definition Address: A040 000C / 002C Table 299: DMA Peripheral Chip Select register BBus Bridge Interrupt Status register Address: A040 1000 Table 300: BBus Bridge Interrupt Status register BBus Bridge Interrupt Enable register Table 301: BBus Bridge Interrupt Enable register bit definition Page About the BBus DMA controllers DMA context memory DMA buffer descriptor Figure 84: DMA buffer descriptor Table 303: DMA buffer descriptor definition Table 303: DMA buffer descriptor definition Table 304: Peripheral bit fields: Serial controller UART RX mode Table 305: Peripheral bit fields: Serial controller SPI RX mode Table 306: Peripheral bit fields: Serial controller UART TX mode Table 307: Peripheral bit fields: Serial controller SPI TX mode Table 308: Peripheral bit fields: USB device controller Table 309: Peripheral bit fields: IEEE 1284 controller DMA channel assignments DMA Control and Status registers within each DMA module. The offsets allow address bits [08:05] to encode the DMA channel number. Table 311: DMA Control and Status register address map DMA Buffer Descriptor Pointer Table 311: DMA Control and Status register address map Address: DMA1 Page DMA Control register Table 313: BBus DMA Control register bit definition DMA Status/Interrupt Enable register Page Table 314: DMA Status/Interrupt Enable register bit definition Page Page Page BBus Utility Control and Status registers Table 315: BBus Utility configuration and status register address map Master Reset register Address: 9060 0000 Table 316: Master Reset register GPIO Configuration registers GPIO Configuration Register #5 Address: 9060 0020 Table 318: GPIO Configuration Register #6 Table 319: GPIO Configuration Register #5 GPIO Configuration Register #4 Address: 9060 001C GPIO Configuration Register #3 Address: 9060 0018 Table 320: GPIO Configuration Register #4 GPIO Configuration Register #2 Address: 9060 0014 Table 321: GPIO Configuration register #3 Table 322: GPIO Configuration Register #2 GPIO Configuration Register #1 Address: 9060 0010 GPIO Configuration register options Table 323: GPIO Configuration Register #1 Table 324: GPIO Configuration register options GPIO Control registers Address: 9060 0034 Table 324: GPIO Configuration register options Table 325: GPIO Control Register #2 GPIO Control Register #1 Address: 9060 0030 Table 325: GPIO Control Register #2 Table 326: GPIO Control Register #1 GPIO Status registers Address: 9060 0044 Table 326: GPIO Control Register #1 Table 327: GPIO Status Register #2 GPIO Status Register #1 Address: 9060 0040 Table 327: GPIO Status Register #2 Table 328: GPIO Status Register #1 BBus Monitor register Address: 9060 0050 Write 0 to this register. Table 328: GPIO Status Register #1 BBus DMA Interrupt Status register Address: 9060 0060 Table 329: BBus DMA Interrupt Status register BBus DMA Interrupt Enable register Address: 9060 0064 Table 329: BBus DMA Interrupt Status register Table 330: BBus DMA Interrupt Enable register USB Configuration register Address: 9060 0070 Table 330: BBus DMA Interrupt Enable register Table 331: USB Configuration register Endian Configuration register Table 332: Endian Configuration register ARM Wake-up register Address: 9060 0090 Table 332: Endian Configuration register Table 333: ARM Wake-up register Page I2C Master/Slave Interface T Physical I2C bus I2C external addresses I2C command interface Locked interrupt driven mode Master module and slave module commands Bus arbitration I2C registers Command Transmit Data register Address: 9050 0000 Table 337: CMD_REG and TX_DATA_REG Status Receive Data register Address: 9050 0000 Table 338: STATUS_REG and RX_DATA_REG Master Address register Address: 9050 0004 Table 339: Master Address register (7-bit and 10-bit) Slave Address register Address: 9050 0008 Table 340: Slave Address register (7-bit and 10-bit) Configuration register Interrupt Codes Table 342: Master/slave interrupt codes Software driver Flow charts Flow charts Master module (normal mode, 16-bit) Slave module (normal mode, 16-bit) Page Page LCD features Programmable parameters LCD panel resolution LCD panel support Number of colors LCD power up and power down sequence support LCD controller functional overview Clocks Signals and interrupts LCD Controller Figure 86: LCD controller block diagram AHB interface AHB master and slave interfaces Dual DMA FIFOs and associated control logic Pixel serializer AHB interface Figure 87: LBLP, DMA FIFO output bits 31:16 Figure 88: LBLP, DMA FIFO output bits 15:0 LCD Controller Figure 89: BBBP, DMA FIFO output bits 31:16 Figure 90: BBBP, DMA FIFO output bits 15:0 AHB interface Figure 91: LBBP, DMA FIFO output bits 31:16 Figure 92: LBBP, DMA FIFO output bits 15:0 DMA FIFO OUTPUT BITS RAM palette Grayscaler Upper and lower panel formatters Panel clock generator Timing controller Generating interrupts External pad interface signals LCD panel signal multiplexing details Table 346: LCD STN panel signal multiplexing Table 346: LCD STN panel signal multiplexing Table 347: LCD TFT panel signal multiplexing Table 347: LCD TFT panel signal multiplexing Table 348: RGB bit alignment according to TFT interface size (one color shown) Registers LCDTiming0 Address: A080 0000 The LCDTiming0 register controls the horizontal axis panel, which includes: Table 350: LCDTiming0 register Page LCDTiming1 Address: A080 0004 The LCDTiming1 register controls the vertical axis panel, which includes: Table 352: LCDTiming1 register LCDTiming2 register Table 352: LCDTiming1 register Address: A080 0008 The LCDTiming2 register provides controls for the timing signals. Page Table 353: LCDTiming2 register Page LCDTiming3 LCDUPBASE and LCDLPBASE Page LCDINTRENABLE Address: A080 0018 Table 356: LCDLPBASE register LCDControl register Address: A080 001C The LCDControl register controls the mode in which the LCD controller operates. Table 357: LCDINTRENABLE register Table 358: LCDControl register Page Page LCDStatus register Address: A080 0020 The LCDStatus register provides raw interrupt status. set. to that bit. Writing a 0 has no effect. LCDInterrupt register LCDUPCURR and LCDLPCURR LCDPalette register Page Table 363: LCDPalette register Interrupts MBERRORINTR Master bus error interrupt VCOMPINTR Vertical compare interrupt Page Page Page Page Bit-rate generator UART mode Transmit FIFO interface Receive FIFO interface Page Serial port performance Serial port control and status registers Table 365: Serial channel B & A configuration registers Table 366: Serial channel C & D configuration registers Serial Channel B/A/C/D Control Register A Address: 9020 0000 / 0040 9030 0000 / 0040 There are two Serial Channel B/A/C/D Control Registers A within each two-channel Page Page Serial Channel B/A/C/D Control Register B Address: 9020 0004 / 0044 9030 0004 / 0044 There are two Serial Channel B/A/C/D Control Registers B within each two-channel Page Table 368: Serial Channel B/A/C/D Control Register B Serial Channel B/A/C/D Status Register A Table 368: Serial Channel B/A/C/D Control Register B Address: 9020 0008 / 0048 9030 0008 / 0048 Page Page Page Page Page Page Serial Channel B/A/C/D Bit-rate register Address: 9020 000C / 004C 9030 000C / 004C Page Page Page Table 371: Bit-rate examples for X1_SYS_OSC/2 Table 372: Bit-rate examples for X1_SYS_OSC/4 Serial Channel B/A/C/D FIFO Data register Table 372: Bit-rate examples for X1_SYS_OSC/4 Address: 9020 0010 / 0050 9030 0010 / 0050 Serial Channel B/A/C/D Receive Buffer GAP Timer Table 374: Serial Channel B/A/C/D Receive Buffer GAP Timer Serial Channel B/A/C/D Receive Character GAP Timer Table 375: Serial Channel B/A/C/D Receive Character GAP Timer Serial Channel B/A/C/D Receive Match register Address: 9020 001C / 005C 9030 001C / 005C Table 376: Serial Channel B/A/C/D Receive Match register Serial Channel B/A/C/D Receive Match MASK register Serial Channel B/A/C/D Flow Control register Address: 9020 0034 / 0074 9030 0034 / 0074 Table 378: Serial Channel B/A/C/D Flow Control register Serial Channel B/A/C/D Flow Control Force register Address: 9020 0038 / 0078 9030 0038 / 0078 Table 379: Serial Channel B/A/C/D Flow Control Force register Page Page Page Page Bit-rate generator SPI mode SPI modes FIFO management Transmit FIFO interface Receive FIFO interface Page Serial port performance Serial port control and status registers Table 382: Serial channel B & A configuration registers Table 383: Serial channel C & D configuration registers Serial Channel B/A/C/D Control Register A Address: 9020 0000 / 0040 9030 0000 / 0040 There are two Serial Channel B/A/C/D Control Registers A within each two-channel Page Page Serial Channel B/A/C/D Control Register B Address: 9020 0004 / 0044 9030 0004 / 0044 There are two Serial Channel B/A/C/D Control Registers B within each two-channel Table 385: Serial Channel B/A/C/D Control Register B Serial Channel B/A/C/D Status Register A Address: 9020 0008 / 0048 9030 0008 / 0048 Page Page Serial Channel B/A/C/D Bit-rate register Address: 9020 000C / 004C 9030 000C / 004C Page Page Page Page Serial Channel B/A/C/D FIFO Data register Page Page Page Page Requirements Requirements BBus Interface IEEE 1284 Bus Two components are required to run the IEEE 1284 peripheral-to-host interface: Figure 95: IEEE 1284 peripheral port control module Clock divider. Required to generate the 1284-port operating clock from the Compatibility mode Page ECP mode X Data and command FIFOs IEEE 1284 negotiation BBus slave and DMA interface BBus slave and DMA interface register map Table 390: 1284 Control and Status registers IEEE 1284 General Configuration register Address: 9040 0000 Table 390: 1284 Control and Status registers Table 391: IEEE 1284 General Configuration register Interrupt Status and Control register Page Table 392: Interrupt Status and Control register FIFO Status register Address: 9040 0008 Page Forward Command FIFO Read register Address: 9040 000C Table 394: Forward Command FIFO Read register Forward Data FIFO Read register Address: 9040 0010 Reverse FIFO Write register/Reverse FIFO Write Register Last Address: 9040 001C / 9040 0020 Both registers are 32 bits. Table 396: Reverse Data FIFO Write register/Reverse Data FIFO Write Register Last Forward Command DMA Control register Forward Data DMA Control register Printer Data Pins register Port Status register, host Address: 9040 0104 Table 399: pd Printer Data Pins register Table 400: psr Port Status register, host Port Control register Address: 9040 0108 Table 401: pcr Port Control register Port Status register, peripheral Address: 9040 010C Feature Control Register A Address: 9040 0114 Feature Control Register A enables buffer trigger levels for printer port operations. Feature Control Register B Address: 9040 0118 You must set bit[0] to 1 in Feature Control Register B. Bits[31:01] are reserved. Interrupt Enable register Address: 9040 011C Table 404: fei Interrupt Enable register Master Enable register Address: 9040 0120 The Master Enable register enables different IEEE 1284 modes and automatic transfer modes. Table 405: fem Master enable register BBus slave and DMA interface Extensibility Byte Requested by Host Address: 9040 0124 Extended Control register Address: 9040 0128 The Extended Control register enables additional core features. Interrupt Status register Address: 9040 012C Table 407: ecr Extended Control register Table 408: sti Interrupt Status register Pin Interrupt Mask register Address: 9040 0134 The Pin Interrupt Mask register enables IEEE 1284 pin interrupts. Table 408: sti Interrupt Status register Table 409: msk Pin Interrupt Mask register Pin Interrupt Control register Address: 9040 0138 The Pin Interrupt Control register configures IEEE 1284 pin interrupt edge levels. Table 410: pit Pin Interrupt Control register Granularity Count register Forward Address register Core Phase (IEEE1284) register Address: 9040 0178 Table 413: Core Phase register Page Page Page USB module architecture Page USB device block Control and status Packet and data flow Logical and physical endpoints Slew rates Host block Control and status Packet data flow USB device endpoint Transmission error handling Handling USB-IN packet errors Handling USB-OUT packet errors USB block registers USB Global registers Global Control and Status register Address: 9010 0000 Table 417: Global Control and Status register Device Control and Status register Address: 9010 0004 Table 417: Global Control and Status register Table 418: Device Control and Status register Global Interrupt Enable register Address: 9010 000C Table 419: Global Interrupt Enable register Global Interrupt Status register Table 419: Global Interrupt Enable register Address: 9010 0010 Page Page Device IP Programming Control/Status register Address: 9010 0014 Table 421: Device IP Programming Control/Status register USB host block registers Reserved bits USB host block register address map HCRevision register Table 422: USB Host Block registers address map Address: 9010 1000 HcControl regis te r Page Page HcCommandStatus register Address: 9010 1008 Page Table 425: HcCommandStatus register HcInterruptStatus register Table 426: HcInterruptStatus register HcInterruptEnable register Table 427: HcInterruptEnable register HcInterruptDisable register Table 428: HcInterruptDisable register HcHCCA register HcPeriodCurrentED register HcControlHeadED register Address: 9010 1020 Table 430: HcPeriodCurrentED HcControlCurrentED register Address: 9010 1024 Table 431: HcControlHeadED register HcBulkHeadED register Address: 9010 1028 Table 432: HcControlCurrentED register HcBulkCurrentED register Table 434: HcBulkCurrentED register HcDoneHead register HcFmInterval register HcFmRemaining register Address: 9010 1038 Table 436: HcFmInterval register HcFmNumber register Address: 9010 103C Table 437: HcFmRemaining register HcPeriodicStart register Address: 9010 1040 Table 438: HcFmNumber register Table 439: HcPeriodicStart register HcLsThreshold register Address: 9010 1044 Table 439: HcPeriodicStart register Root hub partition registers HcRhDescriptorA register Address: 9010 1048 Table 441: HcRhDescriptorA register HcRhDescriptorB register Address: 9010 104C Table 442: HcRhDesdcriptorB register HcRhStatus register Address: 9010 1050 The HcRhStatus register has two parts: Table 442: HcRhDesdcriptorB register Page Page HcRhPortStatus[1] register Page Page Page Page Page USB Device Block registers Table445 provides the addresses of the USB Device Block registers. Table 445: USB Device Block registers address map Device Descriptor/Setup Command register Address: 9010 2000 Endpoint Descriptor #0#11 registers Address: 9010 2004 / 2008 / 200C / 2010 / 2014 / 2018 / 201C / 2020 / 2024 / 2028 / 202C / 2030 Table 446: Endpoint Descriptor register (for endpoint descriptors 011) USB Device Endpoint FIFO Control and Data registers Table 447: USB Device Endpoint FIFO Control registers address map Table 446: Endpoint Descriptor register (for endpoint descriptors 011) Table 447: USB Device Endpoint FIFO Control registers address map Table 448: FIFO to DMA channel to endpoint map FIFO Interrupt Status registers Table 449: USB device endpoint status FIFO Interrupt Status 0 register Address: 9010 3000 Address: 9010 3010 FIFO Interrupt Status 1 register Table 450: FIFO Interrupt Status 0 register Table 451: FIFO Interrupt Status 1 register FIFO Interrupt Status 2 register Address: 9010 3020 Table 452: FIFO Interrupt Status 2 register Table 451: FIFO Interrupt Status 1 register Table 452: FIFO Interrupt Status 2 register FIFO Interrupt Status 3 register Address: 9010 3030 Table 453: FIFO Interrupt Status 3 register FIFO Interrupt Enable registers Address: 9010 3004 Table 454: FIFO Interrupt Enable 0 register FIFO Interrupt Enable 1 register Address: 9010 3014 Table 455: FIFO Interrupt Enable 1 register FIFO Interrupt Enable 2 register Address: 9010 3024 Table 456: FIFO Interrupt Enable 2 register Table 455: FIFO Interrupt Enable 1 register FIFO Interrupt Enable 3 register Address: 9010 3034 Table 456: FIFO Interrupt Enable 2 register FIFO Packet Control registers Table 457: FIFO Interrupt Enable 3 register FIFO Status and Control registers Table 458: FIFO Packet Control registers Page Table 459: FIFO Status and Control registers Page Page Page Page Electrical characteristics The NS9750 operates at a 1.5V core, with 3.3V I/O ring voltages. Table 461: Recommended operating conditions Absolute maximum ratings Permanent device damage can occur if the absolute maximum ratings are exceeded for even an instant. Maximum power dissipation Table462 shows the maximum power dissipation, including sleep mode information, for I/O and core. The next table shows typical power dissipation for I/O and core. Typical power dissipation Table 462: NS9750 power dissipation DC electrical characteristics Table 464: USB DC electrical inputs USB DC electrical inputs Inputs All electrical inputs are 3.3V interface. Outputs All electrical outputs are 3.3V interface. Table 466: USB DC electrical outputs USB DC electrical outputs Table 464: USB DC electrical inputs Reset and edge sensitive input timing requirements Page Power sequencing Power sequencing OR Use these requirements for power sequencing: NS9750 Power Sequencing Block Diagram - 5V or 3V source Memory timing Table 467: SDRAM timing parameters SDRAM burst read (16-bit) Figure 104: SDRAM burst read (16-bit) timing SDRAM burst read (16-bit), CAS latency = 3 Figure 105: SDRAM burst read (16-bit), CAS latency = 3 timing SDRAM burst write (16-bit) Figure 106: SDRAM burst write (16-bit) timing SDRAM burst read (32-bit) Figure 107: SDRAM burst read (32-bit) timing SDRAM burst read (32-bit), CAS latency = 3 Figure 108: SDRAM burst read (32-bit), CAS latency = 3 timing SDRAM burst write (32-bit) Figure 109: SDRAM burst write (32-bit) timing SDRAM load mode Figure 110: SDRAM load mode timing SDRAM refresh mode Figure 111: SDRAM refresh mode timing Clock enable timing Figure 112: Clock enable timing Table468 describes the values shown in the SRAM timing diagrams (Figure 113 through Figure 118). Table 468: SRAM timing parameters Static RAM read cycles with 0 wait states 806 Static RAM asynchronous page mode read, WTPG = 1 Figure 114: Static RAM asynchronous page mode read, WTPG = 1 timing WTPG = 1 WTRD = 2 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, Static RAM read cycle with configurable wait states 808 Static RAM sequential write cycles Figure 116: Static RAM sequential write cycles WTWR = 0 WWEN = 0 will always be high. Static RAM write cycle Figure 117: Static RAM write cycle WTWR = 0 WWEN = 0 will always be high. Static write cycle with configurable wait states Figure 118: Static write cycle with configurable wait states WWEN = from 0 to 15 Slow peripheral acknowledge timing This table describes the values shown in the slow peripheral acknowledge timing diagrams. Table 469: Slow peripheral acknowledge timing parameters Slow peripheral acknowledge read Slow peripheral acknowledge write Ethernet timing Table470 describes the values shown in the Ethernet timing diagrams (Figure 119 and Figure 120). Table 470: Ethernet timing characteristics Ethernet timing Ethernet MII timing Figure 119: Ethernet MII timing Ethernet RMII timing Figure 120: Ethernet RMII timing PCI timing Table 471: PCI timing characteristics Table 472: CardBus timing characteristics PCI timing Internal PCI arbiter timing Figure 121: Internal PCI arbiter timing PCI bu r s t w r ite fro m NS9750 t iming Figure 122: PCI burst write from NS9750 timing The functional timing for trdy_n and devsel_n shows the fastest possible response from the target. PCI bu r s t r e a d f rom NS9750 tim i n g Figure 123: PCI burst read from NS9750 timing PCI bu r s t w r ite to NS9750 t i m i n g Figure 124: PCI burst write to NS9750 timing PCI timing PCI bu r s t r e a d to NS9750 tim i n g Figure 125: PCI burst read to NS9750 timing PCI clock timing Figure 126: pci_clock_out timing Figure 127: pci_clk_in timing I2C timing Table473 describes the values shown in the I2C timing diagram (Figure 128). Figure 128: I2C timing Table 473: I2C timing parameters LCD timing Table474 describes the values shown in the LCD timing diagrams (Figure 129 through Figure 135). Table 474: LCD timing parameters Horizontal timing for STN displays Figure 129: Horizontal timing for STN displays Vertical timing for STN displays Figure 130: Vertical timing parameters for STN displays Horizontal timing for TFT displays Figure 131: Horizontal timing parameters for TFT displays Vertical timing for TFT displays HSYNC vs VSYNC timing for STN displays Figure 133: HSYNC vs VSYNC timing for STN displays HSYNC vs VSYNC timing for TFT displays Figure 134: HSYNC vs VSYNC timing for TFT displays LCD output timing SPI timing Table475 describes the values shown in the SPI timing diagrams (Figure 136 through Figure 139). Table 475: SPI timing parameters 829 B/A/C/D Control Register A. SPI master mode 0 and 1: 2-byte transfer Figure 136: SPI master mode 0 and 1 (2-byte transfer) SPI master mode 2 and 3: 2-byte transfer Figure 137: SPI master mode 2 and 3 (2-byte transfer) SPI timing SPI slave mode 0 and 1: 2-byte transfer Figure 138: SPI slave mode 0 and 1 (2-byte transfer) SPI slave mode 2 and 3: 2-byte transfer Figure 139: SPI slave mode 2 and 3 (2-byte transfer) IEEE 1284 timing Table476 describes the values shown in the IEEE 1284 timing diagram (Figure 140). Figure 140: IEEE 1284 timing with BBus clock at 50 MHZ and GCR set to 25 IEEE 1284 timing example Table 476: IEEE 1284 timing parameters USB timing Table 478: USB low speed timing parameters Table 477: USB full speed timing parameters USB differential data timing Figure 141: USB differential data USB full speed load timing Figure 142: USB full speed load USB low speed load Figure 143: USB low speed load Reset and hardware strapping timing JTAG timing Table480 describes the values shown in the JTAG timing diagram (Figure 145). Figure 145: JTAG timing Table 480: JTAG timing parameters Clock timing USB crystal/external oscillator timing LCD input clock timing Table482 describes the values shown in the LCD input clock timing diagram (Figure 147). Figure 147: LCD input clock timing Table 482: LCD input clock timing parameters System PLL bypass mode timing Table483 describes the values shown in the system PLL bypass mode timing diagram (Figure 148). Figure 148: System PLL bypass mode timing Table 483: System PLL bypass mode timing parameters Page Page Page Packaging 0.6 + 0.1 Figure 150: NS9750 side and bottom views // 0.35 0.20 2.46 MAX Figure 151 shows the layout of the NS9750, for use in setting up the board. NS9750, 352 BGA R Top View, Balls Facing Down B V Product specifications These tables provide additional information about the NS9750. Table 485: NS9750 materials sheet Table 484: NS9750 ROHS specifications Table 485: NS9750 materials sheet Index Numerics A B C mode.</Emphasis> D map. controller. peripheral transfers. memory transfers. E module. Ethernet MAC F G counters. H I J L M Page N O P Page Page R S Page Page Page T U V W