Digi NS9750 Table 106: Address mapping for 64M SDRAM (2Mx32, BRC), Table 105: Address mapping for 16M SDRAM (2Mx8, BRC)

Dynamic memory controller
176 NS9750 Hardware Reference
Table105 shows the outputs from the memory controller and the corresponding
inputs to the 16M SDRAM (2Mx8, pin 13 used as bank select).
Table106 shows the outputs from the memory controller and the corresponding
inputs to the 64M SDRAM (2Mx32, pins 13 and 14 used as bank selects).
Output address
(ADDROUT)Memory device connections AHB address to row address AHB address to column address
14---
13 BA 22 22
12---
11---
10 10/AP 21 AP
99 20 -
8 8 19 10
77 18 9
66 17 8
55 16 7
44 15 6
33 14 5
22 13 4
11 12 3
00 11 2
Table 105: Address mapping for 16M SDRAM (2Mx8, BRC)
Output address
(ADDROUT)Memory device connections AHB address to row address AHB address to column address
14 BA1 21 21
13 BA0 22 22
12---
Table 106: Address mapping for 64M SDRAM (2Mx32, BRC)