Samsung M471B1G73AH0 manuals

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M471B1G73AH0
datasheet
- Rev. 1.0, Jul. 2010
- 204pin Unbuffered SODIMM based on 4Gb A-die
  - 78FBGA with Lead-Free & Halogen-Free (RoHS compliant)
    - Unbuffered SODIMM datasheet DDR3 SDRAM
    - 3Table Of Contents
      - 204pin Unbuffered SODIMM based on 4Gb A-die
    - 41. DDR3 Unbuffered SODIMM Ordering Information
    - 2. Key Features
    - 3. Address Configuration
    - 54. x64 DIMM Pin Configurations (Front side/Back Side)
      - Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
    - 65. Pin Description
    - 76. Input/Output Functional Description
    - 87. Function Block Diagram:
      - 7.1 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
        D11
        D3
        D1
        D9
        D0
        D8
        D2
        D10
        D4
        D12
        D14
        D6
        D15
        D7
        D13
        D5
    - 98. Absolute Maximum Ratings
      - 8.1 Absolute Maximum DC Ratings
      - 8.2 DRAM Component Operating Temperature Range
    - 9. AC & DC Operating Conditions
      - 9.1 Recommended DC Operating Conditions (SSTL-15)
        Symbol Parameter rating Unit NOTE TOPER Operating Temperature Range 0 to 95 C 1, 2, 3
    - 1010. AC & DC Input Measurement Levels
      - 10.1 AC & DC Logic Input Levels for Single-ended Signals
        [ Table 1 ] Single-ended AC & DC input levels for Command and Address
        [ Table 2 ] Single-ended AC & DC input levels for DQ and DM
      - 1110.2 VREF Tolerances.
        V
      - 1210.3 AC and DC Logic Input Levels for Differential Signals
        10.3.1 Differential Signals Definition
        10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS)
        1310.3.3 Single-ended Requirements for Differential Signals
        VDD or VDDQ VSEH min VDD/2 or VDDQ/2 VSEL max
        V
        VSS or VSSQ
        V
        CK or DQS time
        10.3.4 Differential Input Cross Point Voltage
      - 1410.4 Slew Rate Definition for Single Ended Input Signals
      - 10.5 Slew rate definition for Differential Input Signals
    - 1511. AC & DC Output Measurement Levels
      - 11.1 Single Ended AC and DC Output Levels
      - 11.2 Differential AC and DC Output Levels
      - 11.3 Single-ended Output Slew Rate
      - 1611.4 Differential Output Slew Rate
    - 1712. DIMM IDD specification definition
      - Symbol Description
    - 1913. IDD SPEC Table
      - M471B1G73AH0 : 8GB (1Gx64) Module
    - 2014. Input/Output Capacitance
      - 14.1 2Rx8 2GB SODIMM
    - 2115. Electrical Characteristics and AC timing
      - 15.1 Refresh Parameters by Device Density
      - 15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
      - 15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
        2515.3.1 Speed Bin Table Notes
        Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
    - 2616. Timing Parameters by Speed Grade
      - [ Table 17 ] Timing Parameters by Speed Bin
      - 28[ Table 17 ] Timing Parameters by Speed Bin (Cont.)
      - 2916.1 Jitter Notes
      - 3016.2 Timing Parameter Notes
        ZQCorrection (TSens x Tdriftrate) + (VSens x Vdriftrate)
        128ms
        0.5 (1.5 x 1) + (0.15 x 15) = 0.133
        ~ ~
    - 3117. Physical Dimensions :
      - 17.1 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73AH0
        The used device is 512M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B4G0846A - HC**
        Detail BDetail A
        Units : Millimeters