Texas Instruments TMS320C2XX manuals
Computer Equipment > Calculator
When we buy new device such as Texas Instruments TMS320C2XX we often through away most of the documentation but the warranty.
Very often issues with Texas Instruments TMS320C2XX begin only after the warranty period ends and you may want to find how to repair it or just do some service work.
Even oftener it is hard to remember what does each function in Calculator Texas Instruments TMS320C2XX is responsible for and what options to choose for expected result.
Fortunately you can find all manuals for Calculator on our side using links below.
Texas Instruments TMS320C2XX Manual
587 pages 3.16 Mb
Preface 3 Read This First12 Contents19 Figures22 Tables24 Examples25 Cautions26 Introduction33 Architectural Overview46 Central Processing Unit63 Memory and I/O Spaces100 Program Control137 Addressing Modes154 Assembly Language InstructionsChapter 7155 7.1 Instruction Set Summary165 7.2 How To Use the Instruction Descriptions173 7.3 Instruction Descriptions175 ABS181 ADDCAdd to Accumulator With Carry Example 1 ADDC DAT300 ;(DP = 6: addresses 0300h037Fh; ;DAT300 is a label for 300h) Example 2 ADDC *,AR4 ;(OVM = 0) 183 ADDSAdd to Accumulator With Sign Extension Suppressed Example 1 ADDS 0 ;(DP = 6: addresses 0300h037Fh) Example 2 ADDS * 185 ADDTAdd to Accumulator With Shift Specified by TREG Example 1 ADDT 127 ;(DP = 4: addresses 0200h027Fh, ;SXM = 0) Example 2 ADDT *,AR4 ;(SXM = 0) 186 ADRKAPAC 190 Table 77. Product Shift Modes198 Figure 71. Bit Numbers and Their Corresponding Bit Codes for BIT Instruction199 BITTest Bit Example 1 BIT 0h,15 ;(DP = 6). Test LSB at 300h Example 2 BIT *,0,AR1 ;Test MSB at 310h, then set ARP = 1 BITT 200 Figure 72. Bit Numbers and Their Corresponding Bit Codes for BITT Instruction201 BITTTest Bit Specified by TREG Example 1 BITT 00h ;(DP = 6) Test bit 14 of data ;at 300h Example 2 BITT * ;Test bit 1 of data at 310h 203 sourcedestination 208 source destination 211 CALA212 CALL213 CC215 CLRCcontrol bit Status Registers ST0 and ST1 217 CMPL218 CMPR219 DMOV220 DMOV Assembly Language Instructions Example 1 DMOV DAT8 ;(DP = 6) Example 2 DMOV *,AR1 221 IDLE222 IN223 IN224 INTR228 LACL229 LACLLoad Low Accumulator and Clear High Accumulator Example 1 LACL 1 ;(DP = 6: addresses 0300h037Fh) Example 2 LACL *,AR4 231 LACT Load Accumulator With Shift Specified by TREG 232 LACT Assembly Language Instructions Example 1 LACT 1 ;(DP = 6: addresses 0300h037Fh, ;SXM = 0) Example 2 LACT *,AR3 ;(SXM = 1) 237 LDPLoad Data Page Pointer Example 1 LDP 127 ;(DP = 511: addresses FF80hFFFFh) Example 2 LDP #0h Example 3 LDP *,AR5 239 LPHLoad Product Register High Word Example 1 LPH DAT0 ;(DP = 4) Example 2 LPH *,AR6 240 Figure 73. LST #0 Operation241 Figure 74. LST #1 Operation245 LTLoad TREG Example 1 LT 24 ;(DP = 8: addresses 0400h047Fh) Example 2 LT *,AR3 247 LTALoad TREG and Accumulate Previous Product Example 1 LTA 36 ;(DP = 6: addresses 0300h037Fh, ;PM =0: no shift of product) Example 2 LTA *,AR5 ;(PM = 0) 248 the data move will not occurLoad TREG, Accumulate Previous Product, and Move Data 249 Words 1Example 1 LTD 126 ;(DP = 7: addresses 0380h03FFh, ;PM = 0: no shift of product). Load TREG, Accumulate Previous Product, and Move Data Assembly Language Instructions 250 Example 2 LTD *,AR3 ;(PM = 0)251 LTP Load TREG and Store PREG in Accumulator 252 LTP Assembly Language Instructions Example 1 LTP 36 ;(DP = 6: addresses 0300h037Fh, Example 2 LTP *,AR5 ;(PM = 0) 253 LTS Load TREG and Subtract Previous Product 254 LTS Assembly Language Instructions Example 1 LTS DAT36 ;(DP = 6: addresses 0300h037Fh, Example 2 LTS *,AR2 ;(PM = 0) 258 Example 1 MAC 0FF00h,02h ;(DP = 6, PM = 0, CNF = 1)Example 2 MAC 0FF00h,*,AR5 ;(PM = 0, CNF = 1) 259 pma, dma, pma, ind 264 MAREvent(s) Addressing mode Affects Addressing mode 265 MAR269 MPYA Multiply and Accumulate Previous Product 270 MPYA Assembly Language Instructions Example 1 MPYA DAT13 ;(DP = 6, PM = 0) Example 2 MPYA *,AR4 ;(PM = 0) 271 MPYS Multiply and Subtract Previous Product 272 MPYS Assembly Language Instructions Example 1 MPYS DAT13 ;(DP = 6, PM = 0) Example 2 MPYS *,AR5 ;(PM = 0) 273 MPYU274 MPYU Assembly Language Instructions Example 1 MPYU 16 ;(DP = 4: addresses 0200h027Fh) Example 2 MPYU *,AR6 276 NEG277 NMI278 NOP285 OUT286 OUT Assembly Language Instructions 287 PAC289 POPPop Top of Stack to Low Accumulator Example POP 291 POPDPop Top of Stack to Data Memory Example 1 POPD DAT10 ;(DP = 8) Example 2 POPD *+,AR1 293 PSHDPush Data-Memory Value Onto Stack Example 1 PSHD 127 ;(DP = 3: addresses 018001FFh) Example 2 PSHD *,AR1 294 PUSH295 RET296 RETC297 ROL298 ROR299 RPT300 RPT Assembly Language Instructions Example 1 RPT DAT127 ;(DP = 31: addresses 0F80h0FFFh) ;Repeat next instruction 13 times. Example 2 RPT *,AR1 ;Repeat next instruction 4096 times. Example 3 RPT #1 ;Repeat next instruction two times. 301 SACHshift2 shift shift2 Store High Accumulator With Shift 302 SACH Assembly Language Instructions Example 1 SACH DAT10,1 ;(DP = 4: addresses 0200h027Fh, ;left shift of 1) Example 2 SACH *+,0,AR2 ;(No shift) 303 SACL Store Low Accumulator With Shift 304 SACL Assembly Language Instructions Example 1 SACL DAT11,1 ;(DP = 4: addresses 0200h027Fh, ;left shift of 1) Example 2 SACL *,0,AR7 ;(No shift) 305 SAR306 SAR Assembly Language Instructions Example 1 SAR AR0,DAT30 ;(DP = 6: addresses 0300h037Fh) Example 2 SAR AR0,*+ 307 SBRK308 SETCcontrol bit Status and Control Registers 310 SFL312 SFR313 SPAC315 SPHStore High PREG Example 1 SPH DAT3 ;(DP = 4: addresses 0200h027Fh, ;PM = 0: no shift) Example 2 SPH *,AR7 ;(PM = 2: left shift of four) 317 SPLStore Low PREG Example 1 SPL DAT5 ;(DP = 4: addresses 0200h027Fh, ;PM = 2: left shift of four) Example 2 SPL *,AR3 ;(PM = 0: no shift) 318 SPLK319 SPLKExample 2 SPLK #1111h,*+,AR4 SPM 320 Table 78. Product Shift Modes321 SQRA Square Value and Accumulate Previous Product 322 SQRA Assembly Language Instructions Example 1 SQRA DAT30 ;(DP = 6: addresses 0300h037Fh, Example 2 SQRA *,AR4 ;(PM = 0) 323 SQRS Square Value and Subtract Previous Product 324 SQRS Assembly Language Instructions Example 1 SQRS DAT9 ;(DP = 6: addresses 0300h037Fh, Example 2 SQRS *,AR5 ;(PM = 0) 326 SST332 SUBB334 SUBC335 SUBS Subtract From Accumulator With Sign Extension Suppressed 336 SUBS Assembly Language Instructions Example 1 SUBS DAT2 ;(DP = 16, SXM = 1) Example 2 SUBS * ;(SXM = 1) 337 SUBT Subtract From Accumulator With Shift Specified by TREG 338 SUBT345 TRAP349 ZALR Zero Low Accumulator and Load High Accumulator With Rounding 350 ZALR Assembly Language Instructions Example 1 ZALR DAT3 ;(DP = 32: addresses 1000h107Fh) Example 2 ZALR *,AR4 351 On-Chip Peripherals369 Synchronous Serial Port399 Asynchronous Serial Port419 TMS320C209436 Register Summary450 TMS320C1x/C2x/C2xx/C5x Instruction Set ComparisonAppendix Benhanced instructions TMS320C5x Users Guide TMS320C2x Users Guide TMS320C1x Users Guide 451 B.1 Using the Instruction Set Comparison Table454 B.2 Enhanced InstructionsTable B2. Summary of Enhanced Instructions 455 B.3 Instruction Set Comparison Table , shift2 lk , shift 465 pma CM control bit 466 2-bit constantTMS320C2x Users Guide 467 1-bit constant , PA dma, PA 468 8-bit constant470 1-bit constant9-bit constant AR, lk , dma, 471 n, dma n, 472 pma, dmapma, pma, dma, pma 473 13-bit constant 474 lk dma, PA , PA 477 pma n 478 AR, dmaAR, 479 control bit 481 n, dma n n, 483 n, cond 486 Program Examples510 Submitting ROM Codes to TI513 Design Considerations for Using XDS510 Emulator538 GlossaryAppendix F A 540 BBreak interrupt bit detect bit Calibrate Bus request pin baud-rate divisor register (BRD). Ccarry bit (C). 542 clock mode bit (MCM)DARAM configuration bit auxiliary register Central processing unit Common object file format. next auxiliary regis- ter data page DP direct addressing data page pointer (DP) CNF bit Dual-access RAM 543 Dprogram-address generation logic. 545 EF 547 Glocal data space interrupt acknowledge signal (IACK) HOLD acknowledge signal Global memory allocation register H I 550 L551 M552 NOOverflow flag bit. Overflow bit (synchronous serial port). PRD Printed circuit board Program address register. overflow mode Overflow mode bit. 553 Pprogram address bus (PAB). program counter (PC). 555 R557 S558 SARAMlatch phase status registers ST0 and ST1 Synchronous serial port control register. FREE bit (timer) FREE bit (asynchronous serial port) FREE bit (synchronous serial port) Stop bit selector External access active strobe Transmit register empty indicator Transmit empty indicator timer divide-down register (TDDR) Timer control register. Transmission complete bit Test/control flag bit sign-extension mode bit (SXM). 559 T561 U562 VW X 564 IndexA 567 Bchoosing an EPROM 4-14 connecting the EPROM 4-15 programming the EPROM 4-16 with external frame sync 9-18 with internal frame sync 9-16 definition 2-3 used in program-memory address genera- tion 5-3 568 CC203/C204 8-5 C209 11-14 to 11-18 C203/C204 8-5 C209 11-14 569 D570 E framing error (FE bit) 10-11 overrun (OE bit) 10-11 burst mode 9-29 continuous mode 9-29 571 Fmaskable interrupts 5-20 nonmaskable interrupts 5-29 requesting INT2 and INT3 5-18 GBIO 8-17 to 8-18 IO0IO3 10-15 to 10-16 IO0IO3 10-15 to 10-16 XF 8-18 C209 clock options 11-14 to 11-18 572 HIinput output asynchronous 10-1 to 10-20 introduction 2-12 synchronous 9-1 to 9-30 C203/C204 4-24 C209 11-9 accessing 4-25 C203/C204 5-21 C209 11-12 575 JK 576 LM description 4-7 to 4-10 pages of (diagram) 4-7 address generation logic 5-2 address sources 5-3 configuration description 2-7 configuration 11-7 description 2-8 configuration introduction 2-8 C209 11-7 577 N578 O579 PC209 clock options 11-14 to 11-18 CLKIN/X2 8-4 CLKMOD 11-14 DIV1 and DIV2 8-5 X1 8-4 BIO 8-17 IO0IO3 10-15 XF 8-18 581 R583 SSee also product shift modes 3-7 585 T587 UW X Z
Also you can find more Texas Instruments manuals or manuals for other Computer Equipment.