Texas Instruments TMS320C2XX Example E3. Key Timing for a Single-Processor System Without Buffering (SPL), Example E4. Key Timing for a Single- or Multiprocessor-System With Buffered Input and Output (SPL)

Emulation Design Considerations
E-19 Design Considerations for Using XDS510 Emulator
Of the following two cases, the worst-case path delay is calculated to deter-
mine the maximum system test clock frequency.
Example E–3. Key Timing for a Single-Processor System Without Buffering (SPL)
tpd TCK-DTMS
tdDTMSmax tdDTCKHmin tsu TTMS
tTCKfactor
(31 ns 2ns 10 ns)
0.4
107.5 ns, or 9.3 MHz
tpd TCK-DTDI
tdTTDO tdDTCKLmax tsu DTDLmin
tTCKfactor
(15 ns 16 ns 7ns )
0.4
9.5 ns, or 10.5 MHz
In this case, the TCK-to-DTMS/DTDL path is the limiting factor.
Example E–4. Key Timing for a Single- or Multiprocessor-System With Buffered Input
and Output (SPL)
tpd(TCK-TDMS)
td(DTMSmax) tDTCKHmin tsu (TTMS) t(bufskew)
tTCKfactor
(31 ns 2ns 10 ns 1.35 ns)
0.4
110.9 ns, or 9.0 MHz
tpd(TCK–DTDI)
td(TTDO) tdDTCKLmax tsu (DTDLmin)td (bufskew)
tTCKfactor
120 ns, or 8.3 MHz
(15 ns 15 ns 7ns 10 ns)
0.4
In this case, the TCK-to-DTDI path is the limiting factor.