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Texas Instruments TMS320C2XX Figure 411.Interrupt Vectors Transferred First During Boot Load

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Boot Loader

4-20

Figure 4–11.Interrupt Vectors Transferred First During Boot Load

8000h

8-bit EPROM

in global data memory 16-bit RAM

in program memory

0000h

003Fh

8001h

Destinationh (00)

Destinationl (00)

Length Nh

Length Nl

8002h

8003h

Interrupt vectors

Program code

Interrupt vectors

Program code

nnnFh

8004h

8083h

8084h

0040h

Contents

Main Page Preface Read This First Architectural Overview Introduction About This Manual How to Use This Manual Page Notational Conventions Information About Cautions Related Documentation From Texas Instruments TMS320C1x/C2x/C2xx/C5x Code Generation Tools Getting Started Guide TMS320C2xx C Source Debugger Users Guide TMS320C2x/C2xx/C5x Optimizing C Compiler Users Guide TMS320C1x/C2x/C2xx/C5x Assembly Language Tools Users Guide Page Related Articles Page Trademarks If You Need Assistance xi Read This First If You Need Assistance. . . World-Wide Web Sites North America, South America, Central America Europe, Middle East, Africa Asia-Pacific Contents Page Describes the operation and use of the TMS320C2xx data-memory addressing modes. Page Describes the operation and control of the TMS320C2xx on-chip synchronous serial port. Describes the operation and control of the TMS320C2xx on-chip asynchronous serial port. Page Page Figures Page Page Tables Page Examples Cautions Introduction Chapter 1 1.1 TMS320 Family 1.1.1 History, Development, and Advantages of TMS320 DSPs Electronic Products Page TMS320 Family 1.1.2 Typical Applications for the TMS320 Family Table 11. Typical Applications for TMS320 DSPs 1.2 TMS320C2xx Generation Table 12. C2xx Generation Summary 1.3 Key Features of the TMS320C2xx Page Architectural Overview Chapter 2 Architectural Overview Figure 21. Overall Block Diagram of the C2xx 2.1 C2xx Bus Structure program address bus data read bus program read bus data-write address bus Figure 22. Bus Structure Block Diagram 2.2 Central Processing Unit 2.2.1 Central Arithmetic Logic Unit (CALU) and Accumulator 2.2.2 Scaling Shifters 2.2.3 Multiplier 2.2.4 Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers Addressing Modes 2.3 Memory and I/O Spaces Table 21. Program and Data Memory on the TMS320C2xx Devices Memory and I/O Space 2.3.1 Dual-Access On-Chip RAM 2.3.2 Single-Access On-Chip Program/Data RAM 2.3.3 Factory-Masked On-Chip ROM 2.3.4 Flash Memory 2.4 Program Control 2.5 On-Chip Peripherals 2.5.1 Clock Generator Wait-State Generator Timer 2.5.2 CLKOUT1-Pin Control (CLK) Register 2.5.5 General-Purpose I/O Pins 2.5.6 Serial Ports Asynchronous Serial Port, Table 22. Serial Ports on the C2xx Devices Synchronous serial port (SSP) 2.6 Scanning-Logic Circuitry Central Processing Unit Chapter 3 Page 3.1 Input Scaling Section Figure 32. Block Diagram of the Input Scaling Section The data read bus (DRDB). The program read bus (PRDB). A constant embedded in the instruction word. Figure 33. Operation of the Input Shifter for SXM = 0 Figure 34. Operation of the Input Shifter for SXM = 1 3.2 Multiplication Section Figure 35. Block Diagram of the Multiplication Section 3.2.1 Multiplier 3.2.2 Product-Scaling Shifter Multiplication Section Table 31. Product Shift Modes for the Product-Scaling Shifter 3.3 Central Arithmetic Logic Section Figure 36. Block Diagram of the Central Arithmetic Logic Section 3.3.1 Central Arithmetic Logic Unit (CALU) 3.3.2 Accumulator Carry bit (C). Overflow mode bit (OVM). Overflow flag bit (OV). Test/control flag bit (TC). Conditional Branches, Calls, and Returns 3.3.3 Output Data-Scaling Shifter Figure 37. Shifting and Storing the High Word of the Accumulator Figure 38. Shifting and Storing the Low Word of the Accumulator Auxiliary Register Arithmetic Unit (ARAU) 3.4 Auxiliary Register Arithmetic Unit (ARAU) Figure 39.ARAU and Related Logic current AR 3.4.1 ARAU and Auxiliary Register Functions Page 3.5 Status Registers ST0 and ST1 Figure 310. Status Register ST0 Figure 311.Status Register ST1 Table 32. Bit Fields of Status Registers ST0 and ST1 Status Registers ST0 and ST1 Table 32. Bit Fields of Status Registers ST0 and ST1 (Continued) . Accumulator Memory and I/O Spaces Chapter 4 4.1 Overview of the Memory and I/O Spaces 4.1.1 Pins for Interfacing to External Memory and I/O Spaces Table 41. Pins for Interfacing With External Memory and I/O Spaces Overview of the Memory and I/O Spaces Table 41. Pins for Interfacing With External Memory and I/O Spaces (Continued) 4.2 Program Memory 4.2.1 Interfacing With External Program Memory Program Memory 4-6 Figure 41. Interface With External Program Memory 4.3 Local Data Memory Figure 42. Pages of Data Memory 4.3.1 Data Page 0 Address Map Table 42. Data Page 0 Address Map 4.3.2 Interfacing With External Local Data Memory Local Data Memory 4-10 Figure 43. Interface With External Local Data Memory 4.4 Global Data Memory Table 43. Global Data Memory Configurations Figure 44. GREG Register Set to Configure 8K for Global Data Memory Figure 45. Global and Local Data Memory for GREG = 11100000 4.4.1 Interfacing With External Global Data Memory Global Data Memory Figure 46. Using 8000hFFFFh for Local and Global External Memory 4.5 Boot Loader Figure 47. Simplified Block Diagram of Boot Loader Operation 4.5.1 Choosing an EPROM 4.5.2 Connecting the EPROM to the Processor Figure 48. Connecting the EPROM to the Processor 4.5.3 Programming the EPROM Interrupt Table Figure 49. Storing the Program in the EPROM 4.5.4 Enabling the Boot Loader 4.5.5 Boot Loader Execution Figure 410. Program Code Transferred From 8-Bit EPROM to 16-Bit RAM Figure 411.Interrupt Vectors Transferred First During Boot Load 4.5.6 Boot Loader Program Page I/O Space 4.6 I/O Space Figure 412. I/O Address Map for the C2xx Table 44. On-Chip Registers Mapped to I/O Space 4.6.1 Accessing I/O Space I/O Space 4-26 Figure 413. I/O Port Interface Circuitry 4.7 Direct Memory Access Using the HOLD Operation Direct Memory Access Using the HOLD Operation Example 41. An Interrupt Service Routine Supporting INT1 and HOLD 4.7.1 HOLD During Reset Figure 414. HOLD Deasserted Before Reset Deasserted Page 4.8 Device-Specific Information 4.8.1 TMS320C203 Address Maps and Memory Configuration Figure 416. C203 Address Map Table 45. C203 Program-Memory Configuration Options Table 46. C203 Data-Memory Configuration Options 4.8.2 TMS320C204 Address Maps and Memory Configuration Figure 417. C204 Address Map Page Table 47. C204 Program-Memory Configuration Options Table 48. C204 Data-Memory Configuration Options Program Control Chapter 5 Program-Address Generation 5-2 5.1 Program-Address Generation Figure 51. Program-Address Generation Block Diagram Table 51. Program-Address Generation Summary 5.1.1 Program Counter (PC) Table 52. Address Loading to the Program Counter 5.1.2 Stack Figure 52. A Push Operation Figure 53. A Pop Operation 5.1.3 Micro Stack (MSTACK) 5.2 Pipeline Operation Figure 54. 4-Level Pipeline Operation 5.3 Branches, Calls, and Returns branch return call Conditional Branches, Calls, and Returns 5.3.3 Unconditional Returns 5.4 Conditional Branches, Calls, and Returns Table 53. Conditions for Conditional Calls and Returns 5.4.1 Using Multiple Conditions Table 54. Groupings of Conditions 5.4.2 Stabilization of Conditions 5.4.3 Conditional Branches 5.4.4 Conditional Calls 5.4.5 Conditional Returns Page 5.5 Repeating a Single Instruction 5.6 Interrupts software interrupt Internal External hardware interrupt 5.6.2 Interrupt Table C209 Interrupts Table 55. C2xx Interrupt Locations and Priorities Interrupts Program Control Table 55. C2xx Interrupt Locations and Priorities (Continued) 5.6.3 Maskable Interrupts Figure 55. INT2/INT3 Request Flow Chart interrupt vector location Nonmaskable Interrupts Figure 56. Maskable Interrupt Operation Flow Chart 5.6.4 Interrupt Flag Register (IFR) C209 Interrupt Registers Figure 57. C2xx Interrupt Flag Register (IFR) Data-Memory Address 0006h To avoid double interrupts, write a 1 to this bit in the interrupt service routine. Direct Memory Access Using The HOLD Operation 5.6.5 Interrupt Mask Register (IMR) C209 Interrupt Registers Figure 58. C2xx Interrupt Mask Register (IMR) Data-Memory Address 0004h 5.6.6 Interrupt Control Register (ICR) Controlling the HOLD/INT1 pin Di- rect Memory Access Using The HOLD Operation Controlling INT2 and INT3 Page Figure 59. C2xx Interrupt Control Register (ICR) I/O-Space Address FFECh Double-edge mode. Single-edge mode. 5.6.7 Nonmaskable Interrupts Hardware nonmaskable interrupts Software interrupts Reset Op- eration Page Figure 510. Nonmaskable Interrupt Operation Flow Chart 5.6.8 Interrupt Service Routines (ISRs) Saving and restoring register values Managing ISRs within ISRs within after 5.6.9 Interrupt Latency Latency for pipeline protection Latency for stack overflow protection Page 5.7 Reset Operation Page Reset Operation Program Control Table 56. Reset Values of On-Chip Registers Mapped to Data Space Table 57. Reset Values of On-Chip Registers Mapped to I/O Space 5.8 Power-Down Mode 5.8.1 Normal Termination of Power-Down Mode after 5.8.2 Termination of Power-Down During a HOLD Operation Addressing Modes Chapter 6 6.1 Immediate Addressing Mode 6.1.1 Examples of Immediate Addressing Example 61. RPT Instruction Using Short-Immediate Addressing Figure 61. Instruction Register Contents for Example 61 Example 62. ADD Instruction Using Long-Immediate Addressing Figure 62. Two Words Loaded Consecutively to the Instruction Register in Example 62 Direct Addressing Mode 6.2 Direct Addressing Mode Figure 63. Pages of Data Memory Figure 64. Instruction Register (IR) Contents in Direct Addressing Mode Figure 65. Generation of Data Addresses in Direct Addressing Mode 6.2.1 Using Direct Addressing Mode 6.2.2 Examples of Direct Addressing Example 63. Using Direct Addressing with ADD (Shift of 0 to 15) Example 64. Using Direct Addressing with ADD (Shift of 16) Example 65. Using Direct Addressing with ADDC 6.3 Indirect Addressing Mode 6.3.1 Current Auxiliary Register current AR 6.3.2 Indirect Addressing Options Table 61. Indirect Addressing Operands Table 61. Indirect Addressing Operands (Continued) 6.3.3 Next Auxiliary Register next AR next auxiliary register Example 66. Selecting a New Current Auxiliary Register 6.3.4 Indirect Addressing Opcode Format Figure 66. Instruction Register Content in Indirect Addressing Table 62. Effects of the ARU Code on the Current Auxiliary Register Indirect Addressing Mode 6-14 Table 63. Field Bits and Notation for Indirect Addressing Instruction Opcode Bits 15 8 7 6 5 4 3 2 1 0 Operand(s) Operation 6.3.5 Examples of Indirect Addressing Example 67. No Increment or Decrement Example 68. Increment by 1 Page 6.3.6 Modifying Auxiliary Register Content Assembly Language Instructions Chapter 7 7.1 Instruction Set Summary Indirect Addressing Mode Table 71. Accumulator, Arithmetic, and Logic Instructions Page Table 71. Accumulator, Arithmetic, and Logic Instructions (Continued) Table 72. Auxiliary Register Instructions Table 73. TREG, PREG, and Multiply Instructions Table 73. TREG, PREG, and Multiply Instructions (Continued) Table 74. Branch Instructions Table 74. Branch Instructions (Continued) Table 75. Control Instructions Table 75. Control Instructions (Continued) Table 76. I/O and Memory Instructions Page 7.2 How To Use the Instruction Descriptions 7.2.1 Syntax Page 7.2.2 Operands 7.2.3 Opcode 7.2.4 Execution 7.2.5 Status Bits 7.2.6 Description 7.2.7 Words 7.2.8 Cycles src, dst, code Wait-State Generator Pipeline 7.2.9 Examples Page 7.3 Instruction Descriptions Page ABS Page Affected by Affects Addressing mode Add to Accumulator Assembly Language Instructions Example 1 ADD 1,1 ;(DP = 6) Example 2 ADD *+,0,AR0 Page Page ADDC Add to Accumulator With Carry Example 1 ADDC DAT300 ;(DP = 6: addresses 0300h037Fh; ;DAT300 is a label for 300h) Example 2 ADDC *,AR4 ;(OVM = 0) Page ADDS Add to Accumulator With Sign Extension Suppressed Example 1 ADDS 0 ;(DP = 6: addresses 0300h037Fh) Example 2 ADDS * Page ADDT Add to Accumulator With Shift Specified by TREG Example 1 ADDT 127 ;(DP = 4: addresses 0200h027Fh, ;SXM = 0) Example 2 ADDT *,AR4 ;(SXM = 0) ADRK Page Page Page APAC Table 77. Product Shift Modes Page B BACC Page BANZ BCND Page BIT Figure 71. Bit Numbers and Their Corresponding Bit Codes for BIT Instruction BIT Test Bit Example 1 BIT 0h,15 ;(DP = 6). Test LSB at 300h Example 2 BIT *,0,AR1 ;Test MSB at 310h, then set ARP = 1 BITT Figure 72. Bit Numbers and Their Corresponding Bit Codes for BITT Instruction BITT Test Bit Specified by TREG Example 1 BITT 00h ;(DP = 6) Test bit 14 of data ;at 300h Example 2 BITT * ;Test bit 1 of data at 310h Page source destination Page Page 7-53 Example 1 BLDD #300h,20h ;(DP = 6) Example 2 BLDD *+,#321h,AR3 Page source destination Block Move From Program Memory to Data Memory Block Move From Program Memory to Data Memory Assembly Language Instructions Example 1 BLPD #800h,00h ;(DP=6) Example 2 BLPD #800h,*,AR7 CALA CALL CC Page CLRC control bit Status Registers ST0 and ST1 Page CMPL CMPR CM DMOV no Data Move in Data Memory DMOV Assembly Language Instructions Example 1 DMOV DAT8 ;(DP = 6) Example 2 DMOV *,AR1 IDLE IN PA ind ,PA PA dma , PA IN Input Data From Port INTR Interrupt Table Page Page Page LACL Events Addressing mode LACL Load Low Accumulator and Clear High Accumulator Example 1 LACL 1 ;(DP = 6: addresses 0300h037Fh) Example 2 LACL *,AR4 Page LACT Load Accumulator With Shift Specified by TREG LACT Assembly Language Instructions Example 1 LACT 1 ;(DP = 6: addresses 0300h037Fh, ;SXM = 0) Example 2 LACT *,AR3 ;(SXM = 1) Page Page Page Page LDP Load Data Page Pointer Example 1 LDP 127 ;(DP = 511: addresses FF80hFFFFh) Example 2 LDP #0h Page LPH Load Product Register High Word Example 1 LPH DAT0 ;(DP = 4) Example 2 LPH *,AR6 Figure 73. LST #0 Operation Figure 74. LST #1 Operation Page Page Page LT Load TREG Example 1 LT 24 ;(DP = 8: addresses 0400h047Fh) Example 2 LT *,AR3 Page LTA Load TREG and Accumulate Previous Product Example 1 LTA 36 ;(DP = 6: addresses 0300h037Fh, ;PM =0: no shift of product) Example 2 LTA *,AR5 ;(PM = 0) the data move will not occur Load TREG, Accumulate Previous Product, and Move Data Words 1 Example 1 LTD 126 ;(DP = 7: addresses 0380h03FFh, ;PM = 0: no shift of product). Load TREG, Accumulate Previous Product, and Move Data 7-97 Assembly Language Instructions Example 2 LTD *,AR3 ;(PM = 0) LTP Load TREG and Store PREG in Accumulator LTP Assembly Language Instructions Example 1 LTP 36 ;(DP = 6: addresses 0300h037Fh, Example 2 LTP *,AR5 ;(PM = 0) LTS Load TREG and Subtract Previous Product LTS Assembly Language Instructions Example 1 LTS DAT36 ;(DP = 6: addresses 0300h037Fh, Example 2 LTS *,AR2 ;(PM = 0) Page Page Multiply and Accumulate Multiply and Accumulate Assembly Language Instructions Example 1 MAC 0FF00h,02h ;(DP = 6, PM = 0, CNF = 1) Example 2 MAC 0FF00h,*,AR5 ;(PM = 0, CNF = 1) pma, dma , pma, ind Page Page Page 7-110 Example 2 MACD 0FF00h,*,AR6 ;(PM = 0, CNF = 1) MAR Event(s) Addressing mode Affects Addressing mode MAR Page Multiply Example 1 MPY DAT13 ;(DP = 8) Multiply 7-115 Assembly Language Instructions Example 2 MPY *,AR2 Example 3 MPY #031h MPYA Multiply and Accumulate Previous Product MPYA Assembly Language Instructions Example 1 MPYA DAT13 ;(DP = 6, PM = 0) Example 2 MPYA *,AR4 ;(PM = 0) MPYS Multiply and Subtract Previous Product MPYS Assembly Language Instructions Example 1 MPYS DAT13 ;(DP = 6, PM = 0) Example 2 MPYS *,AR5 ;(PM = 0) MPYU Multiply Unsigned MPYU Assembly Language Instructions Example 1 MPYU 16 ;(DP = 4: addresses 0200h027Fh) Example 2 MPYU *,AR6 Page NEG Example 3 NEG ;(OVM = 1) NMI NOP Page before Page Page Page OR With Accumulator 7-131 Assembly Language Instructions Example 1 ORDAT8 ;(DP = 8) Example 2 OR*,AR0 Example 3 OR#08111h,8 OUT Output Data to Port OUT Assembly Language Instructions PAC Page POP Pop Top of Stack to Low Accumulator 7-136 Example POP Page POPD Pop Top of Stack to Data Memory Example 1 POPD DAT10 ;(DP = 8) Example 2 POPD *+,AR1 Page PSHD Push Data-Memory Value Onto Stack Example 1 PSHD 127 ;(DP = 3: addresses 018001FFh) Example 2 PSHD *,AR1 PUSH RET RETC ,... ROL ROR RPT Repeat Next Instruction RPT Assembly Language Instructions Example 1 RPT DAT127 ;(DP = 31: addresses 0F80h0FFFh) ;Repeat next instruction 13 times. Example 2 RPT *,AR1 ;Repeat next instruction 4096 times. Example 3 RPT #1 ;Repeat next instruction two times. SACH shift2 shift shift2 Store High Accumulator With Shift SACH Assembly Language Instructions Example 1 SACH DAT10,1 ;(DP = 4: addresses 0200h027Fh, ;left shift of 1) Example 2 SACH *+,0,AR2 ;(No shift) SACL Store Low Accumulator With Shift SACL Assembly Language Instructions Example 1 SACL DAT11,1 ;(DP = 4: addresses 0200h027Fh, ;left shift of 1) Example 2 SACL *,0,AR7 ;(No shift) SAR x, , ind dma SAR Assembly Language Instructions Example 1 SAR AR0,DAT30 ;(DP = 6: addresses 0300h037Fh) Example 2 SAR AR0,*+ SBRK SETC control bit Status and Control Registers Page SFL Page SFR SPAC Page SPH Store High PREG Example 1 SPH DAT3 ;(DP = 4: addresses 0200h027Fh, ;PM = 0: no shift) Example 2 SPH *,AR7 ;(PM = 2: left shift of four) Page SPL Store Low PREG Example 1 SPL DAT5 ;(DP = 4: addresses 0200h027Fh, ;PM = 2: left shift of four) Example 2 SPL *,AR3 ;(PM = 0: no shift) SPLK lk , #lk, ind lk SPLK Example 2 SPLK #1111h,*+,AR4 SPM constant Table 78. Product Shift Modes SQRA Square Value and Accumulate Previous Product SQRA Assembly Language Instructions Example 1 SQRA DAT30 ;(DP = 6: addresses 0300h037Fh, Example 2 SQRA *,AR4 ;(PM = 0) SQRS Square Value and Subtract Previous Product SQRS Assembly Language Instructions Example 1 SQRS DAT9 ;(DP = 6: addresses 0300h037Fh, Example 2 SQRS *,AR5 ;(PM = 0) Page SST Status Registers ST0 and ST1 Page Affected by Affects Addressing mode Subtract From Accumulator Example 1 SUB DAT80 ;(DP = 8: addresses 0400h047Fh, ;SXM=0: sign-extension suppressed) Example 2 SUB *,1,AR0 ;(Left shift by 1, SXM = 0) Subtract From Accumulator 7-177 Assembly Language Instructions Example 3 SUB #8h ;(SXM = 1: sign-extension mode) Example 4 SUB #0FFFh,4 ;(Left shift by four, SXM = 0) Page SUBB Page SUBC SUBS Subtract From Accumulator With Sign Extension Suppressed SUBS Assembly Language Instructions Example 1 SUBS DAT2 ;(DP = 16, SXM = 1) Example 2 SUBS * ;(SXM = 1) SUBT Subtract From Accumulator With Shift Specified by TREG SUBT Assembly Language Instructions Example 1 SUBT DAT127 ;(DP = 5: addresses 0280h02FFh) Example 2 SUBT * Page Table Read Assembly Language Instructions Table Read Example 1 TBLR DAT6 ;(DP = 4: addresses 0200h027Fh) Example 2 TBLR *,AR7 Page Table Write Table Write Assembly Language Instructions Example 1 TBLW DAT5 ;(DP = 32: addresses 1000h107Fh) Example 2 TBLW * TRAP Page Page Page ZALR Zero Low Accumulator and Load High Accumulator With Rounding ZALR Assembly Language Instructions Example 1 ZALR DAT3 ;(DP = 32: addresses 1000h107Fh) Example 2 ZALR *,AR4 On-Chip Peripherals Chapter 8 Control of On-Chip Peripherals 8.1 Control of On-Chip Peripherals CLKOUT1-pin control (CLK) register. Reset Operation , on page 5-33. Table 81. Peripheral Register Locations and Reset Conditions Table 81. Peripheral Register Locations and Reset Conditions (Continued) 8.2 Clock Generator Figure 81. Using the Internal Oscillator Figure 82. Using an External Oscillator 8.2.1 Clock Generator Options Table 82. C2xx Input Clock Modes 2 CLKOUT1 = CLKIN 2 0 0 No Enabled Disabled 8.3 CLKOUT1-Pin Control (CLK) Register Figure 83. C2xx CLK Register I/O-Space Address FFE8h Power-Down Mode 8.4 Timer Figure 84. Timer Functional Block Diagram 8.4.1 Timer Operation Equation 81. Timer Interrupt Rate for Nonzero TDDR and/or PRD 8.4.2 Timer Control Register (TCR) Figure 85. C2xx Timer Control Register (TCR) I/O-Space Address FFF8h dont care Table 83. C2xx Timer Run/Emulation Modes 8.4.3 Timer Counter Register (TIM) and Timer Period Register (PRD) 8.4.4 Setting the Timer Interrupt Rate 8.4.5 The Timer at Hardware Reset 8.5 Wait-State Generator 8.5.1 Generating Wait States With the READY Signal internal C209 Memory and I/O Spaces 8.5.2 Generating Wait States With the C2xx Wait-State Generator Figure 86. C2xx Wait-State Generator Control Register (WSGR) I/O-Space Address FFFCh upper lower Table 84. Setting the Number of Wait States With the C2xx WSGR Bits w 8.6 General-Purpose I/O Pins 8.6.1 Input Pin BIO Figure 87. BIO Timing Diagram Example 8.6.2 Output Pin XF 8.6.3 Input/Output Pins IO0, IO1, IO2, and IO3 Using I/O Pins IO3, IO2, IO1, and IO0 Synchronous Serial Port Chapter 9 9.1 Overview of the Synchronous Serial Port 9.2 Components and Basic Operation Figure 91. Synchronous Serial Port Block Diagram 9.2.1 Signals Table 91. SSP Interface Pins Figure 92. 2-Way Serial Port Transfer With External Frame Sync and External Clock 9.2.2 FIFO Buffers and Registers 9.2.3 Interrupts 9.2.4 Basic Operation Page 9.3 Controlling and Resetting the Port Test Bits dont care Figure 93. Synchronous Serial Port Control Register (SSPCR) I/O-Space Address FFF1h Table 92. Run and Emulation Modes Table 93. Controlling Transmit Interrupt Generation by Writing to Bits FT1 and FT0 Table 94. Controlling Receive Interrupt Generation by Writing to Bits FR1 and FR0 Page 9.3.1 Selecting a Mode of Operation (Bit 1 of the SSPCR) 9.3.2 Selecting Transmit Clock Source and Transmit Frame Sync Source (Bits 2 and 3 of the SSPCR) Table 95. Selecting Transmit Clock and Frame Sync Sources 9.3.3 Resetting the Synchronous Serial Port (Bits 4 and 5 of the SSPCR) 9.3.4 Using Transmit and Receive Interrupts (Bits 811 of the SSPCR) Interrupts 9.4 Managing the Contents of the FIFO Buffers 9.5 Transmitter Operation 9.5.1 Burst Mode Transmission With Internal Frame Sync (FSM = 1, TXM = 1) Figure 94. Burst Mode Transmission With Internal Frame Sync and Multiple Words in the Buffer 9.5.2 Burst Mode Transmission With External Frame Sync (FSM = 1, TXM = 0) Transmitter Operation 9-19 Synchronous Serial Port Figure 95. Burst Mode Transmission With External Frame Sync 9.5.3 Continuous Mode Transmission With Internal Frame Sync (FSM = 0, TXM = 1) Figure 96. Continuous Mode Transmission With Internal Frame Sync 9.5.4 Continuous Mode Transmission with External Frame Sync (FSM=0, TXM=0) Transmitter Operation 9-23 Synchronous Serial Port Figure 97. Continuous Mode Transmission With External Frame Sync 9.6 Receiver Operation 9.6.1 Burst Mode Reception Figure 98. Burst Mode Reception 9.6.2 Continuous Mode Reception Figure 99. Continuous Mode Reception 9.7 Troubleshooting 9.7.1 Test Bits dont care Figure 910. Test Bits in the SSPCR Table 96. Run and Emulation Modes 9.7.2 Burst Mode Error Conditions 9.7.3 Continuous Mode Error Conditions Page Asynchronous Serial Port Chapter 10 10.1 Overview of the Asynchronous Serial Port 10.2 Components and Basic Operation Figure 101. Asynchronous Serial Port Block Diagram 10.2.1 Signals Table 101. Asynchronous Serial Port Interface Pins 10.2.2 Baud-Rate Generator 10.2.3 Registers 10.2.4 Interrupts 10.2.5 Basic Operation Figure 102. Typical Serial Link Between a C2xx Device and a Host CPU 10.3 Controlling and Resetting the Port 10.3.1 Asynchronous Serial Port Control Register (ASPCR) Figure 103. Asynchronous Serial Port Control Register (ASPCR) I/O-Space Address FFF5h Page Page 10.3.2 I/O Status Register (IOSR) Figure 104. I/O Status Register (IOSR) I/O-Space Address FFF6h Page Page 10.3.3 Baud-Rate Divisor Register (BRD) Equation 101. Value Needed in the BRD Table 102. Common Baud Rates and the Corresponding BRD Values 10.3.4 Using Automatic Baud-Rate Detection 10.3.5 Using I/O Pins IO3, IO2, IO1, and IO0 Figure 105. Example of the Logic for Pins IO0IO3 Table 103. Configuring Pins IO0IO3 with ASPCR Bits CIO0CIO3 When pins IO0IO3 are configured as inputs Table 104. Viewing the Status of Pins IO0IO3 With IOSR Bits IO0IO3 and DIO0DIO3 When pins IO0IO3 are configured as outputs 10.3.6 Using Interrupts Page 10.4 Transmitter Operation Figure 106. Data Transmit 10.5 Receiver Operation Figure 107. Data Receive TMS320C209 Chapter 11 11.1 C209 Versus Other C2xx Devices 11.1.1 What Is the Same 11.1.2 What Is Different 11.1.3 Where to Find the Information You Need About the TMS320C209 Page 11.2 C209 Memory and I/O Spaces C209 Memory and I/O Spaces Figure 111.C209 Address Maps Page Table 111. C209 Program-Memory Configuration Options Table 112. C209 Data-Memory Configuration Options Table 113. C209 On-Chip Registers Mapped to I/O Space C209 Interrupts 11.3 C209 Interrupts Table 114. C209 Interrupt Locations and Priorities C209 Interrupts TMS320C209 Table 114. C209 Interrupt Locations and Priorities (Continued) 11.3.1 C209 Interrupt Registers Figure 112.C209 Interrupt Flag Register (IFR) Data-Memory Address 0006h Figure 113.C209 Interrupt Mask Register (IMR) Data-Memory Address 0004h 11.3.2 IACK Pin 11.4 C209 On-Chip Peripherals 11.4.1 C209 Clock Generator Options Table 115. C209 Input Clock Modes 2 CLKOUT1 = CLKIN 11.4.2 C209 Timer Control Register (TCR) Figure 114.C209 Timer Control Register (TCR) I/O Address FFFCh 11.4.3 C209 Wait-State Generator Figure 115.C209 Wait-State Generator Control Register (WSGR) I/O Address FFFFh Register Summary Addresses and Reset Values A.1 Addresses and Reset Values Table A1. Reset Values of the Status Registers Table A2. Addresses and Reset Values of On-Chip Registers Mapped to Data Space Table A3. Addresses and Reset Values of On-Chip Registers Mapped to I/O Space Page A.2 Register Descriptions Status Register ST0 Status Register ST1 C2xx Interrupt Flag Register (IFR) Except C209 Data-Memory Address 0006h Interrupt Flag Register (IFR) C209 Data-Memory Address 0006h Interrupt Mask Register (IMR) Except C209 Data-Memory Address 0004h Interrupt Mask Register (IMR) C209 Data-Memory Address 0004h Interrupt Control Register (ICR) I/O Address FFECh Single-edge mode. Double-edge mode. Timer Control Register (TCR) Except C209 I/O Address FFF8h Timer Control Register (TCR) C209 I/O Address FFFCh Wait-State Generator Control Register (WSGR) Except C209 I/O Address FFFCh Wait-State Generator Control Register (WSGR) C209 I/O Address FFFFh CLK Register I/O Address FFE8h Synchronous Serial Port Control Register (SSPCR) I/O Address FFF1h Asynchronous Serial Port Control Register (ASPCR) I/O Address FFF5h I/O Status Register (IOSR) I/O Address FFF6h TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison Appendix B enhanced instructions TMS320C5x Users Guide TMS320C2x Users Guide B.1 Using the Instruction Set Comparison Table B.1.1 An Example of a Table Entry Description 5x 2xx, B.1.2 Symbols and Acronyms Used in the Table The following table lists the instruction set symbols and acronyms used throughout this chapter: Table B1. Symbols and Acronyms Used in the Instruction Set Summary Description B.2 Enhanced Instructions Table B2. Summary of Enhanced Instructions B.3 Instruction Set Comparison Table , shift2 lk , shift Page Page Page Page Page Page Page Page Page pma CM control bit 2-bit constant TMS320C2x Users Guide 1-bit constant , PA dma, PA 8-bit constant Page 1-bit constant 9-bit constant AR, lk , dma, n, dma n, pma, dma pma, pma, dma, pma 13-bit constant lk dma, PA , PA Page Page pma n AR, dma AR, control bit Page n, dma n n, Page n, cond Page Page Program Examples Appendix C C.1 About These Program Examples c203.cmd test.out test.asm Figure C1. Procedure for Generating Executable Files Table C1.Shared Programs in This Appendix Table C2.Task-Specific Programs in This Appendix About These Program Examples Table C2.Task-Specific Programs in This Appendix (Continued) C.2 Shared Program Code Example C1. Generic Command File (c203.cmd) Example C2. Header File With I/O Register Declarations (init.h) Example C3. Header File With Interrupt Vector Declarations (vector.h) C.3 Task-Specific Program Code Example C4. Implementing Simple Delay Loops (delay.asm) Example C5. Testing and Using the Timer (timer.asm) Example C6. Testing and Using Interrupt INT1 (intr1.asm) Example C7. Implementing a HOLD Operation (hold.asm) Example C8. Testing and Using Interrupts INT2 and INT3 (intr23.asm) Example C9. Asynchronous Serial Port Transmission (uart.asm) Example C9. Asynchronous Serial Port Transmission (uart.asm) (Continued) Example C10. Loopback to Verify Transmissions of Asynchronous Serial Port (echo.asm) Page Page Example C12. Testing and Using Asynchronous Serial Port Delta Interrupts (bitio.asm) Example C12. Testing and Using Asynchronous Serial Port Delta Interrupts(bitio.asm) Example C13. Synchronous Serial Port Continuous Mode Transmission (ssp.asm) Page Example C14. Using Synchronous Serial Port With Codec Device (ad55.asm) C.4 Introduction to Generating Boot Loader Code TMS320C1x/C2x/C2xx/C5x Assembly Language Tools Users Guide Introduction to Generating Boot Loader Code Example C15. Linker Command File Example C16. Hex Conversion Utility Command File Submitting ROM Codes to TI Appendix D Submitting ROM Codes to TI Figure D1. TMS320 ROM Code Submittal Flow Chart Page Design Considerations for Using XDS510 Emulator Appendix E JTAG 3/5V JTAG, E.1 Designing Your Target Systems Emulator Connector (14-Pin Header) your target system must have a 14-pin header Figure E1. 14-Pin Header Signals and Header Dimensions Designing Your Target Systems Emulator Connector (14-Pin Header) Table E1. 14-Pin Header Signal Descriptions E.2 Bus Protocol E.3 Emulator Cable Pod Figure E2. Emulator Cable Pod Interface E.4 Emulator Cable Pod Signal Timing Figure E3. Emulator Cable Pod Timings Table E2. Emulator Cable Pod Timing Parameters E.5 Emulation Timing Calculations Example E1. Key Timing for a Single-Processor System Without Buffers Example E2. Key Timing for a Single- or Multiple-Processor System With Buffered Input and Output Page E.6 Connections Between the Emulator and the Target System E.6.1 Buffering Signals Figure E4. Emulator Connections Without Signal Buffering Figure E5. Emulator Connections With Signal Buffering Connections Between the Emulator and the Target System E-12 E.6.2 Using a Target-System Clock Figure E6. Target-System-Generated Test Clock E.6.3 Configuring Multiple Processors Figure E7. Multiprocessor Connections E.7 Physical Dimensions for the 14-Pin Emulator Connector Figure E8. Pod/Connector Dimensions Physical Dimensions for the 14-Pin Emulator Connector Figure E9. 14-Pin Connector Dimensions E.8 Emulation Design Considerations E.8.1 Using Scan Path Linkers Advanced Logic and Bus Interface Logic Data Book Figure E10. Connecting a Secondary JTAG Scan Path to a Scan Path Linker E.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL) Example E3. Key Timing for a Single-Processor System Without Buffering (SPL) Example E4. Key Timing for a Single- or Multiprocessor-System With Buffered Input and Output (SPL) E.8.3 Using Emulation Pins Emulation Design Considerations E-21 Figure E11. EMU0/1 Configuration to Meet Timing Requirements of Less Than 25 ns proces- sor halted Figure E12. Suggested Timings for the EMU0 and EMU1 Signals Emulation Design Considerations E-23 m Figure E14. EMU0/1 Configuration Without Global Stop E.8.4 Performing Diagnostic Applications Advanced Logic and Bus Interface Logic Data Book Figure E15. TBC Emulation Connections for n JTAG Scan Paths Glossary Appendix F A Page B Break interrupt bit detect bit Calibrate Bus request pin Page clock mode bit (MCM) DARAM configuration bit auxiliary register Central processing unit Common object file format. D program-address generation logic. Page E F FIFO receive-interrupt bits FE bit FIFO transmit-interrupt bits. Transmit frame synchronization pin. Receive frame synchronization pin. G local data space interrupt acknowledge signal (IACK) HOLD acknowledge signal Global memory allocation register Page interrupt service routine (ISR) interrupt mode bit (INTM) L M N O Overflow flag bit. Overflow bit (synchronous serial port). PRD P program address bus (PAB). program counter (PC). Page R Page S SARAM latch phase status registers ST0 and ST1 Synchronous serial port control register. FREE bit (timer) T Page U V W X Page Index A Page Page B choosing an EPROM 4-14 connecting the EPROM 4-15 programming the EPROM 4-16 with external frame sync 9-18 with internal frame sync 9-16 definition 2-3 used in program-memory address genera- tion 5-3 C C203/C204 8-5 C209 11-14 to 11-18 C203/C204 8-5 C209 11-14 D C203 4-33 C209 11-8 E framing error (FE bit) 10-11 overrun (OE bit) 10-11 burst mode 9-29 continuous mode 9-29 F maskable interrupts 5-20 nonmaskable interrupts 5-29 requesting INT2 and INT3 5-18 G BIO 8-17 to 8-18 IO0IO3 10-15 to 10-16 IO0IO3 10-15 to 10-16 XF 8-18 H I input output asynchronous 10-1 to 10-20 introduction 2-12 synchronous 9-1 to 9-30 Page Page J K L M description 4-7 to 4-10 pages of (diagram) 4-7 address generation logic 5-2 address sources 5-3 N O P C209 clock options 11-14 to 11-18 CLKIN/X2 8-4 CLKMOD 11-14 DIV1 and DIV2 8-5 X1 8-4 BIO 8-17 IO0IO3 10-15 XF 8-18 Page R Page S See also product shift modes 3-7 Page T Page U W C203/C204 8-14 to 8-17 X Z