Xilinx Spartan-3E 1600E manuals
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Xilinx Spartan-3E 1600E Manual
168 pages 9.55 Mb
2 Revision HistoryThe following table shows the revision history for this document. 3 Table of Contents9 About This Guide11 Introduction and OverviewChoose the Starter Kit Board for Your NeedsSpartan-3E FPGA Features and Embedded Processing Functions Learning Xilinx FPGA, CPLD, and ISE Development Software Basics Advanced Spartan-3 Generation Development Boards 12 Key Components and Features13 Design Trade-OffsConfiguration Methods Galore! Voltages for all Applications Chapter 2 15 Switches, Buttons, and Knob21 Clock Sources22 Clock ConnectionsVol tag e Co nt ro l 50 MHz On-Board Oscillator Auxiliary Clock Oscillator Socket SMA Clock Input or Output Connector UCF Constraints Chapter 4 25 FPGA Configuration Options43 Character LCD Screen55 VGA Display Port61 RS-232 Serial PortsChapter 7: RS-232 Serial Ports R Figure 7-1: RS-232 Serial Ports 62 ORChapter 8 65 PS/2 Mouse/Keyboard Port71 Digital to Analog Converter (DAC)77 Analog Capture Circuit85 Intel StrataFlash Parallel NOR Flash PROMSpartan-3E FPGAFigure 11-1: Connections to Intel StrataFlash Flash Memory Intel StrataFlash CoolRunner-II CPLD SPI Serial Flash ADC DAC Platform Flash LCD Header 86 StrataFlash Connections89 Shared ConnectionsCharacter LCD Xilinx XC2C64A CPLD SPI Data Line88 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide Chapter 11: Intel StrataFlash Parallel NOR Flash PROM R 90 AddressFigure 11-3: UCF Location Constraints for StrataFlash Data I/Os Figure 11-2: UCF Location Constraints for StrataFlash Address Inputs Data Control 91 Setting the FPGA Mode Select PinsChapter 12 93 SPI Serial Flash107 DDR SDRAMFigure 13-1: FPGA Interface to Micron 512 Mbit DDR SDRAM All DDR SDRAM interface signals are terminated. MT46V32M16 (32Mx16) 108 DDR SDRAM Connections109 DDR SDRAM ConnectionsTabl e 1 3 - 1: FPGA-to-DDR SDRAM Connections (Continued) Chapter 13: DDR SDRAM R 110 AddressFigure 13-3: UCF Location Constraints for DDR SDRAM Data I/Os Figure 13-2: UCF Location Constraints for DDR SDRAM Address Inputs Data 111 ControlReserve FPGA VREF Pins Chapter 14 113 10/100 Ethernet Physical Layer Interface117 Expansion Connectors129 XC2C64A CoolRunner-II CPLD133 DS2432 1-Wire SHA-1 EEPROM135 Appendix A Schematics136 FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header138 RS-232 Ports, VGA Port, and PS/2 Port142 Voltage Regulators144 FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections146 FPGA I/O Banks 0 and 1, Oscillators148 FPGA I/O Banks 2 and 3150 Power Supply Decoupling152 XC2C64A CoolRunner-II CPLD154 Linear Technology ADC and DAC 158 Buttons, Switches, Rotary Encoder, and Character LCD 163 Appendix B Example User Constraints File (UCF)
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